Patents by Inventor P. Hugo Lamarche

P. Hugo Lamarche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for reconfiguring a programmable logic device
    Patent number: 7518396
    Abstract: A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: April 14, 2009
    Assignee: Xilinx, Inc.
    Inventors: Venu M. Kondapalli, Wei Guang Lu, P. Hugo Lamarche
  • Yield-enhancing methods of providing a family of scaled integrated circuits
    Patent number: 7491576
    Abstract: An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: February 17, 2009
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh, Raymond C. Pang, Bruce E. Talley, Paul Ying-Fung Wu
  • Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
    Patent number: 7345507
    Abstract: A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 18, 2008
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh, Raymond C. Pang, Bruce E. Talley, Paul Ying-Fung Wu