Patents by Inventor P. Jeffrey Ungar

P. Jeffrey Ungar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972187
    Abstract: Methods for reticle enhancement technology include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array (FSA). The FSA is an array of sampled values of the smooth function, which is a continuous differentiable function. Methods also include providing a continuous tone mask (CTM), wherein the CTM is used to produce the predicted wafer pattern, the predicted wafer pattern spanning an entire design area.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 30, 2024
    Assignee: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 11953824
    Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: April 9, 2024
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20240086607
    Abstract: Methods and systems for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. An optimized mask is calculated, wherein the optimized mask is generated by a first trained neural network using the target wafer patter. The calculating is performed for each tile in the plurality of tiles including its halo region.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Akira Fujimura, Ajay Baranwal, Suhas Pillai
  • Patent number: 11783110
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 10, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20230288796
    Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20230289510
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Patent number: 11693306
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 4, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20230205961
    Abstract: Methods for reticle enhancement technology include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array (FSA). The FSA is an array of sampled values of the smooth function, which is a continuous differentiable function. Methods also include providing a continuous tone mask (CTM), wherein the CTM is used to produce the predicted wafer pattern, the predicted wafer pattern spanning an entire design area.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Applicant: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 11620425
    Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 4, 2023
    Assignee: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Hironobu Matsumoto
  • Publication number: 20230034170
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20230035090
    Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, P. Jeffrey Ungar, Nagesh Shirali
  • Publication number: 20220180036
    Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Applicant: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Hironobu Matsumoto
  • Patent number: 11301610
    Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: April 12, 2022
    Assignee: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Hironobu Matsumoto
  • Publication number: 20210141988
    Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.
    Type: Application
    Filed: January 20, 2021
    Publication date: May 13, 2021
    Applicant: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Hironobu Matsumoto
  • Patent number: 10909294
    Abstract: Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 2, 2021
    Assignee: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Publication number: 20200279065
    Abstract: Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Application
    Filed: May 13, 2020
    Publication date: September 3, 2020
    Applicant: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 10657213
    Abstract: Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignee: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 10401435
    Abstract: A system for tracking the capacity of a battery in a portable electronic device is described. While the portable electronic device remains plugged in to a power adapter, the system estimates the capacity of the battery by performing the following operations. The system measures a first open-circuit voltage for the battery while the battery rests at a first state of charge. Next, the system causes the battery to transition to a second state of charge. While the battery transitions to the second state of charge, the system integrates a current through the battery to determine a net change in charge for the battery. Next, the system measures a second open-circuit voltage for the battery while the battery rests at the second state of charge. Finally, the system estimates a capacity for the battery based on the first open-circuit voltage, the second open-circuit voltage and the net change in charge. This capacity measurement is repeated and the multiple results are fit to a line.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: September 3, 2019
    Assignee: Apple Inc.
    Inventors: Nils E. Mattisson, P. Jeffrey Ungar, Thomas C. Greening, Jeffrey G. Koller
  • Publication number: 20190197213
    Abstract: Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicant: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 10044210
    Abstract: Some embodiments of the present invention provide a system that adaptively charges a battery, wherein the battery is a lithium-ion battery which includes a transport-limiting electrode governed by diffusion, an electrolyte separator and a non-transport-limiting electrode. During operation, the system determines a lithium surface concentration at an interface between the transport-limiting electrode and the electrolyte separator based on a diffusion time for lithium in the transport-limiting electrode. Next, the system calculates a charging current or a charging voltage for the battery based on the determined lithium surface concentration. Finally, the system applies the charging current or the charging voltage to the battery.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 7, 2018
    Assignee: Apple Inc.
    Inventors: Thomas C. Greening, P. Jeffrey Ungar, William C. Athas