Patents by Inventor P. Kannan Srinivasagam

P. Kannan Srinivasagam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Active termination circuit with an enable/disable
    Patent number: 6541998
    Abstract: A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: April 1, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Rajesh Manapat, P. Kannan Srinivasagam
  • Active termination circuit with an enable/disable
    Publication number: 20020149390
    Abstract: A termination circuit for use on a conductor of a transmission line. The termination circuit generally comprises a first, second, third and fourth transistor. The first transistor may have (i) a first drain node couplable to the conductor, (ii) a first source node couplable to a first power source presenting a first reference voltage, and (iii) a first gate node. The second transistor may have (i) a second drain node couplable to the conductor, (ii) a second source node couplable to a second power source presenting a second reference voltage, and (iii) a second gate node. The third transistor (i) may have a third source node coupled to the first gate node and (ii) may be configured to bias the first gate node to a first voltage below the first reference voltage. The fourth transistor (i) may have a fourth source node coupled to the second gate node and (ii) may be configured to bias the second gate node to a second voltage above the second reference voltage.
    Type: Application
    Filed: April 17, 2001
    Publication date: October 17, 2002
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventors: Rajesh Manapat, P. Kannan Srinivasagam