Patents by Inventor P Keong Or

P Keong Or has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20230251702
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 10, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: Yen-Cheng LIU, P. Keong OR, Krishnakanth V. SISTLA, Ganapati SRINIVASA
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 11144108
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20210064117
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Yen-Cheng LIU, P. Keong OR, Krishnakanth V. SISTLA, Ganapati SRINIVASA
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20170017286
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20170017292
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 30, 2016
    Publication date: January 19, 2017
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20160195913
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 17, 2015
    Publication date: July 7, 2016
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 9367112
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: June 14, 2016
    Assignee: INTEL CORPORATION
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth V. Sistla, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20150127962
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH V. SISTLA, GANAPATI SRINIVASA
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 8966299
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20140164799
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Inventors: YEN-CHENG LIU, P. KEONG OR, KRISHNAKANTH SISTLA, GANAPATI SRINIVASA
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 8700933
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 15, 2014
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
    Publication number: 20130254572
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 26, 2013
    Inventors: YEN-CHENG LIU, P KEONG OR, KRISHNAKANTH SISTLA, GANAPATI SRINIVASA
  • Optimizing power usage by processor cores based on architectural events
    Patent number: 8473766
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • Optimizing power usage by factoring processor architectural events to PMU
    Patent number: 8412970
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY PROCESSOR CORES BASED ON ARCHITECTURAL EVENTS
    Publication number: 20130031400
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 31, 2013
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • Optimizing Power Usage By Factoring Processor Architectural Events To PMU
    Publication number: 20120089850
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 12, 2012
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth Sistla, Ganapati Srinivasa
  • Optimizing power usage by processor cores based on architectural events
    Patent number: 8117478
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistia, Ganapati Srinivasa
  • OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECUTRAL EVENTS TO PMU
    Publication number: 20080162972
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth Sistia, Ganapati Srinivasa