Abstract: A sense amplifier for sensing data from a pair of complementary bit lines. A bistable circuit is coupled to the bit lines through a pair of transistors. During the beginning of a sensing cycle, the transistors conduct allowing the bistable circuit to begin sensing the data on the lines. However, before the sense amplifier reaches one of its two stable states, the pair transistors cease conducting and isolate the bistable circuit from the bit lines. In this manner, the load associated with the bit lines is removed from the bistable circuit allowing it to more quickly sense data.

Abstract: An improved static memory is described which, when used in a dual port cache memory simplifies write cycles by providing latching of decoded address signals which are used in a subsequent memory cycle for writing. Improved logic is described which allows the propagation of data at the rate .function. with timing signals of frequency 1/2.function.. An improved sense amplifier which is isolated from the column lines is the array is used.