Patents by Inventor P. PRABHU

P. PRABHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250240251
    Abstract: Techniques for management of a dejitter buffer for network communication. A system includes ports to receive emulated traffic transmitted over a packet network, a central memory pool, a controller to allocate memory from the central memory pool dejitter buffers, and an arbiter to arbitrate read and write access from the ports to the central memory pool for the of dejitter buffers. A portion of the central memory pool is allocated as a respective dejitter buffer for each of the plurality of ports, based on a transmission rate associated with each respective port. The controller is capable of allocating any portion of the central memory pool as the dejitter buffer for any respective port, and the controller is configured to, during operation, dynamically change the portion of the central memory pool allocated as the dejitter buffer for a given port.
    Type: Application
    Filed: January 24, 2024
    Publication date: July 24, 2025
    Inventors: Sundeep P. PRABHU, Raghupathi SOMASHEKARAPPA, Luca DELLA CHIESA, Christian SCHMUTZER
  • Publication number: 20250009573
    Abstract: This invention delivers bandages of equal size attached to a wax paper roll. Each bandage incorporates a Tab to pull it off the wax paper for use to cover and protect small wounds. The Tab also facilitates pulling the bandage off one's skin when needed.
    Type: Application
    Filed: July 9, 2023
    Publication date: January 9, 2025
    Inventor: RAM P PRABHU
  • Patent number: 11132231
    Abstract: Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mehulkumar J. Patel, Krishna P. Prabhu, Guha Prasad Venkataraman
  • Patent number: 10682588
    Abstract: An aspect of the present disclosure includes a multi-stage compressor having a low pressure compressor stage and a high pressure compressor stage operable for compressing a working fluid. An integrated device including a heat exchanger directly connected to a combination unit is operable for reducing pressure pulsations, cooling and separating moisture in a first compressed flow stream and a second compressed flow stream discharged from the low pressure stage and the high pressure stage respectively. A first pressure pulsation dampener, a first moisture separator, a second pressure pulsation dampener and a second moisture separator are integrally formed within the combination unit.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 16, 2020
    Assignee: Ingersoll-Rand Industrial U.S., Inc.
    Inventors: Hardik Vinodbhai Gohel, P. Prabhu, Mahesh Kumar.K.R, Vishal Umashanker Gupta, Shambhu M Vaghani
  • Publication number: 20190361715
    Abstract: Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Inventors: MEHULKUMAR J. PATEL, KRISHNA P. PRABHU, GUHA PRASAD VENKATARAMAN
  • Patent number: 10423429
    Abstract: Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mehulkumar J. Patel, Krishna P. Prabhu, Guha Prasad Venkataraman
  • Publication number: 20190205146
    Abstract: Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 4, 2019
    Inventors: MEHULKUMAR J. PATEL, KRISHNA P. PRABHU, GUHA PRASAD VENKATARAMAN
  • Publication number: 20190111359
    Abstract: An aspect of the present disclosure includes a multi-stage compressor having a low pressure compressor stage and a high pressure compressor stage operable for compressing a working fluid. An integrated device including a heat exchanger directly connected to a combination unit is operable for reducing pressure pulsations, cooling and separating moisture in a first compressed flow stream and a second compressed flow stream discharged from the low pressure stage and the high pressure stage respectively. A first pressure pulsation dampener, a first moisture separator, a second pressure pulsation dampener and a second moisture separator are integrally formed within the combination unit.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Inventors: HARDIK VINODBHAI GOHEL, P. PRABHU, MAHESH KUMAR.K.R, VISHAL UMASHANKER GUPTA, SHAMBHU M. VAGHANI
  • Publication number: 20030081728
    Abstract: An object of the present invention is to provide a circuit for generating a pair of well-balanced positive and negative dc high voltages, and an X-ray generator including such a high-voltage generation circuit. The X-ray generator includes a transformer, a pair of rectifier-type dc high-voltage generation circuits, and an X-ray tube. The transformer transfers an ac voltage, which is applied to a primary winding thereof and stepped up, from a single secondary winding thereof that has one terminal thereof grounded. The pair of rectifier-type dc high-voltage generation circuits generates positive and negative dc high voltages according to an ac voltage developed at the other terminal of the secondary winding. The positive dc high voltage is applied to the anode of the X-ray tube, while the negative dc high voltage is applied to the cathode thereof.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 1, 2003
    Inventors: Biju S. Nathan, Ravindra P. Prabhu, Balasubramannian Kandankumarath
  • Publication number: 20030081727
    Abstract: It is an object to provide an X-ray generating apparatus of an integrate type, which permits easy alignment of an X-ray tube and easy insulation against high voltages and which has an X-ray shielding means superior in thermal conductivity. A screw through hole and pin through holes corresponding respectively to a screw hole and plural pin holes formed in an end face of a base portion of an X-ray tube are formed in an abutment face of a bracket against which the end face of the base portion of the X-ray tube comes into abutment, and a screw and plural pins are inserted respectively from the bracket side into the screw hole and plural pin holes in the X-ray tube through the screw through hole and the pin through holes, thereby mounting the X-ray tube to the bracket. The bracket is formed by an integral structure of FR4. An X-ray tube container which receives the X-ray tube therein is constituted by copper alloy plates with lead incorporated therein.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 1, 2003
    Inventors: Balasubramannian Kandankumarath, Biju S. Nathan, Ravindra P. Prabhu, Lijo Joseph Thandiackal
  • Patent number: 6229672
    Abstract: An air bearing slider for a magnetic head is defined by a leading edge and a trailing edge and has a central longitudinal axis extending from the leading edge to the trailing edge. A pair of side pads, and a center pad between the side pads that is disposed substantially on the center axis, are formed on the air bearing surface of the slider. A first central recess having a T-shaped configuration is etched to a first depth, preferably in the range of 5-30 micro-inches with reference to the air bearing surface. A second major recess portion is etched to a second depth in the range of 60-150 micro-inches. The air bearing surface is configured for high load applications and maintains a flat flying height profile. The configured slider is particularly useful with small size sliders, such as picosliders.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: May 8, 2001
    Assignee: Read-Rite Corporation
    Inventors: Christopher A. Lee, Ciuter Chang, Pablo G. Levi, Pravin P. Prabhu, Manuel Anaya-Dufresne
  • Patent number: 5280439
    Abstract: In an apparatus and method for computing inverses and square roots, a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: January 18, 1994
    Assignee: Weitek Corporation
    Inventors: S. M. Quek, Larry Hu, Jnyaneshwar P. Prabhu, Frederick A. Ware
  • Patent number: 5245564
    Abstract: In an apparatus and method for computing inverses and square roots a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: September 14, 1993
    Assignee: Weitek Corporation
    Inventors: S. M. Quek, Larry Hu, Jnyaneshwar P. Prabhu, Frederick A. Ware