Patents by Inventor Pär Westlund
Pär Westlund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10462267Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: GrantFiled: May 31, 2016Date of Patent: October 29, 2019Assignee: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Patent number: 9635145Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.Type: GrantFiled: May 12, 2014Date of Patent: April 25, 2017Assignee: Marvell International Ltd.Inventors: Gunnar Nordmark, Kurt Thomas Boden, Lars-Olof Svensson, Par Westlund
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Publication number: 20160277549Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: May 31, 2016Publication date: September 22, 2016Applicant: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Publication number: 20150215204Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Applicant: Marvell World Trade Ltd.Inventors: Hakan Zeffer, Jakob Carlstrom, Par Westlund, Johan Back, Ronny Nilsson
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Patent number: 9001828Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: GrantFiled: March 21, 2011Date of Patent: April 7, 2015Assignee: Marvell World Trade Ltd.Inventors: Håkan Zeffer, Jakob Cärlstrom, Pär Westlund, Johan Bäck, Ronny Nilsson
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Patent number: 8995263Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.Type: GrantFiled: May 21, 2013Date of Patent: March 31, 2015Assignee: Marvell World Trade Ltd.Inventors: Kurt Thomas Boden, Par Westlund
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Publication number: 20140358886Abstract: A pipeline of memory banks is configured to store and retrieve a forwarding address by distributing portions of the address across the memory banks and subsequently searching for the distributed values. A first value of the address is recoverable by searching for a value, stored by a first memory bank, by consuming a predetermined number of bits of a data unit from a data packet. If present, a subsequent value of the address is recoverable by searching another memory bank of the pipeline for a value of the address contained by a node of a linked list. The pipeline recovers the address by combining value found at the first memory bank with the value found by the node of the linked list at the other memory bank.Type: ApplicationFiled: June 4, 2014Publication date: December 4, 2014Inventors: Par WESTLUND, Lars-Olof SVENSSON
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Publication number: 20140247835Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: Marvell International Ltd.Inventors: Gunnar Nordmark, Kurt Thomas Boden, Lars-Olof Svensson, Par Westlund
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Patent number: 8725900Abstract: The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.Type: GrantFiled: April 3, 2003Date of Patent: May 13, 2014Assignee: Marvell International Ltd.Inventors: Gunnar Nordmark, Thomas Boden, Lars-Olaf Svensson, Par Westlund
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Publication number: 20130315259Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.Type: ApplicationFiled: May 21, 2013Publication date: November 28, 2013Applicant: Marvell World Trade Ltd.Inventors: Kurt Thomas Boden, Par Westlund
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Publication number: 20120243538Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: XELERATED ABInventors: Håkan Zeffer, Jakob Carlström, Pär Westlund, Johan Bäck, Ronny Nilsson
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Patent number: 7397798Abstract: Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the second register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.Type: GrantFiled: May 21, 2001Date of Patent: July 8, 2008Assignee: Xelerated ABInventors: Lars-Olov Svensson, Thomas Stromqvist, Gunnar Nordmark, Par Westlund, Joachim Roos
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Publication number: 20060155771Abstract: The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.Type: ApplicationFiled: April 3, 2003Publication date: July 13, 2006Inventors: Gunnar Nordmark, Thomas Boden, Lars-Olof Svensson, Par Westlund
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Patent number: 7010673Abstract: Apparatus (3) for processing pipelined data, comprises a storage unit and at least one logic unit (11) for executing operations on a block (4) of data. The storage means comprises an instruction table (12a) comprising at least one instruction, and the at least one logic unit (11) is in at least one pipelined processing stage adapted to receive the block (4) and a first instruction (13a) of the at least one instruction and execute the first instruction (13a). The invention also relates to a method for processing pipelined data, a module (1) for processing pipelined data, an integrated circuit (15), a circuit board assembly (16), a computer unit (22) and a pipelined processing system.Type: GrantFiled: May 21, 2001Date of Patent: March 7, 2006Assignee: Xelerated ABInventors: Lars-Olov Svensson, Joachim Roos, Thomas Strömqvist, Pär Westlund, Peter Holm
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Publication number: 20040215620Abstract: Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the first register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.Type: ApplicationFiled: May 7, 2004Publication date: October 28, 2004Inventors: Lars-Olov Svensson, Thomas Stromqvist, Gunnar Nordmark, Par Westlund, Joachim Roos