Patents by Inventor P. Sean Stetson

P. Sean Stetson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Line Driver apparatus
    Patent number: 7130415
    Abstract: A line driver apparatus includes a peak detector operable to receive a data signal and output a first logic signal when the data signal is below a threshold value and output one of a plurality of alternate logic signals when the data signal exceeds the threshold value. The peak detector includes a signal magnitude calculator operable to calculate an amount by which the data signal exceeds the threshold value. The line driver apparatus also includes an amplifier operable to receive a filtered analog data signal and one of a time-delayed first logic signal and one of a time-delayed alternate logic signal, wherein the amplifier operates at a first voltage level upon receiving the time-delayed first logic signal, and the amplifier operates at a voltage level that is increasing toward one of an alternate voltage level upon receiving the time-delayed second logic signal.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Peter J. Melsa, P. Sean Stetson
  • Line driver apparatus
    Publication number: 20040001586
    Abstract: A line driver apparatus includes a peak detector operable to receive a data signal and output a first logic signal when the data signal is below a threshold value and output one of a plurality of alternate logic signals when the data signal exceeds the threshold value. The peak detector includes a signal magnitude calculator operable to calculate an amount by which the data signal exceeds the threshold value. The line driver apparatus also includes an amplifier operable to receive a filtered analog data signal and one of a time-delayed first logic signal and one of a time-delayed alternate logic signal, wherein the amplifier operates at a first voltage level upon receiving the time-delayed first logic signal, and the amplifier operates at a voltage level that is increasing toward one of an alternate voltage level upon receiving the time-delayed second logic signal.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Peter J. Melsa, P. Sean Stetson