Patents by Inventor P. Stephan Bedrosian
P. Stephan Bedrosian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11902016Abstract: A range is determined between two unsynchronized communications terminals in which a first terminal transmits a range request to a second terminal. The first terminal stores a first timestamp in memory corresponding to a time at which the range request message was transmitted. A range response is later received by the first terminal from the second terminal. The range response includes a residence time that characterizes an amount of time the second terminal required to send the range response after receiving the range request. The first terminal later stores a second timestamp in memory corresponding to a time at which the range response was received. Based on the second timestamp minus the first timestamp and the residence time, a roundtrip time for the range request is calculated. This roundtrip time can be used to calculate a distance between the first terminal and the second terminal based on the roundtrip time.Type: GrantFiled: November 30, 2021Date of Patent: February 13, 2024Assignee: MITRE CorporationInventor: P. Stephan Bedrosian
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Publication number: 20230171013Abstract: A range is determined between two unsynchronized communications terminals in which a first terminal transmits a range request to a second terminal. The first terminal stores a first timestamp in memory corresponding to a time at which the range request message was transmitted. A range response is later received by the first terminal from the second terminal. The range response includes a residence time that characterizes an amount of time the second terminal required to send the range response after receiving the range request. The first terminal later stores a second timestamp in memory corresponding to a time at which the range response was received. Based on the second timestamp minus the first timestamp and the residence time, a roundtrip time for the range request is calculated. This roundtrip time can be used to calculate a distance between the first terminal and the second terminal based on the roundtrip time.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventor: P. Stephan Bedrosian
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Patent number: 9124380Abstract: To test the timing-recovery process of a receiving (i.e., slave) node in a packet-based network, a packet filter is configured in a test configuration that already contributes a natural delay distribution to the packet flow arriving at the slave node. The resulting delay distribution of the arriving packet flow is the combination of that natural delay distribution and the effects of the packet filter, which deterministically or statistically reduces the number of packets with delays within the anchor value window arriving at the slave node (i.e., received packets having packet delays within the slave node's anchor value window). The packet filter can be adjusted to test the slave node's timing-recovery process for a wide variety of packet-flow conditions (e.g., different rates of packets with delays within the anchor value window).Type: GrantFiled: March 12, 2013Date of Patent: September 1, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: P. Stephan Bedrosian
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Patent number: 8976778Abstract: In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.Type: GrantFiled: October 19, 2012Date of Patent: March 10, 2015Assignee: LSI CorporationInventor: P. Stephan Bedrosian
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Patent number: 8774197Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.Type: GrantFiled: May 3, 2012Date of Patent: July 8, 2014Assignee: Agere Systems LLCInventor: P. Stephan Bedrosian
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Publication number: 20140153591Abstract: To test the timing-recovery process of a receiving (i.e., slave) node in a packet-based network, a packet filter is configured in a test configuration that already contributes a natural delay distribution to the packet flow arriving at the slave node. The resulting delay distribution of the arriving packet flow is the combination of that natural delay distribution and the effects of the packet filter, which deterministically or statistically reduces the number of packets with delays within the anchor value window arriving at the slave node (i.e., received packets having packet delays within the slave node's anchor value window). The packet filter can be adjusted to test the slave node's timing-recovery process for a wide variety of packet-flow conditions (e.g., different rates of packets with delays within the anchor value window).Type: ApplicationFiled: March 12, 2013Publication date: June 5, 2014Inventor: P. Stephan Bedrosian
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Patent number: 8462819Abstract: An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays.Type: GrantFiled: March 23, 2010Date of Patent: June 11, 2013Assignee: LSI CorporationInventor: P. Stephan Bedrosian
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Patent number: 8446896Abstract: In certain embodiments, a slave node in a packet network achieves time synchronization with a master node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.Type: GrantFiled: December 13, 2010Date of Patent: May 21, 2013Assignee: LSI CorporationInventor: P. Stephan Bedrosian
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Patent number: 8411705Abstract: An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times.Type: GrantFiled: March 24, 2010Date of Patent: April 2, 2013Assignee: LSI CorporationInventor: P. Stephan Bedrosian
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Patent number: 8401025Abstract: In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (DOE(i)) using a window technique that selects the larger of (i) the maximum delay-offset value (DOP) in the previous window and (ii) the maximum delay-offset value so far (DOM) in current window. This windowing technique can be implemented without having to store all of the individual values over a specified window size, as in a conventional sliding window technique. This windowing technique can be used to find extreme (i.e., either maximum or minimum) values for applications other than ACR systems.Type: GrantFiled: April 28, 2010Date of Patent: March 19, 2013Assignee: LSI CorporationInventor: P. Stephan Bedrosian
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Publication number: 20120218986Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.Type: ApplicationFiled: May 3, 2012Publication date: August 30, 2012Applicant: AGERE SYSTEMS INC.Inventor: P. Stephan Bedrosian
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Patent number: 8213436Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.Type: GrantFiled: February 12, 2009Date of Patent: July 3, 2012Assignee: Agere Systems Inc.Inventor: P. Stephan Bedrosian
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Publication number: 20110267946Abstract: In one embodiment, an adaptive clock recovery (ACR) system generates a current delay-offset estimate value (DOE(i)) using a window technique that selects the larger of (i) the maximum delay-offset value (DOP) in the previous window and (ii) the maximum delay-offset value so far (DOM) in current window. This windowing technique can be implemented without having to store all of the individual values over a specified window size, as in a conventional sliding window technique. This windowing technique can be used to find extreme (i.e., either maximum or minimum) values for applications other than ACR systems.Type: ApplicationFiled: April 28, 2010Publication date: November 3, 2011Applicant: LSI CORPORATIONInventor: P. Stephan Bedrosian
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Publication number: 20110261917Abstract: In certain embodiments, a slave node in a packet network achieves time synchronization with a master node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.Type: ApplicationFiled: December 13, 2010Publication date: October 27, 2011Applicant: LSI CORPORATIONInventor: P. Stephan Bedrosian
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Publication number: 20110164627Abstract: An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times.Type: ApplicationFiled: March 24, 2010Publication date: July 7, 2011Applicant: LSI CORPORATIONInventor: P. Stephan Bedrosian
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Publication number: 20110164630Abstract: An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is phase-adjusted, upstream of the ACR subsystem, based on the sign and magnitude of each detected step-delay. As a result, the ACR subsystem is substantially oblivious to the existence of such step-delays.Type: ApplicationFiled: March 23, 2010Publication date: July 7, 2011Applicant: LSI CORPORATIONInventor: P. Stephan Bedrosian
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Patent number: 7848242Abstract: Methods and apparatus for testing adaptive timing characteristics of a packet-based timing protocol are provided. A packet delay variation test sequence is applied to packet-based traffic as the packet-based traffic passes through a packet delay variation generator during transmission between nodes. Adaptive timing characteristics at a node that receives the packet-based traffic are evaluated in accordance with the packet delay variation test sequence.Type: GrantFiled: June 14, 2007Date of Patent: December 7, 2010Assignee: Agere Systems Inc.Inventor: P. Stephan Bedrosian
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Publication number: 20090141725Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.Type: ApplicationFiled: February 12, 2009Publication date: June 4, 2009Applicant: AGERE SYSTEMS INC.Inventor: P. Stephan Bedrosian
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Patent number: 7539200Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.Type: GrantFiled: April 27, 2005Date of Patent: May 26, 2009Assignee: Agere Systems Inc.Inventor: P. Stephan Bedrosian
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Publication number: 20080310447Abstract: Methods and apparatus for testing adaptive timing characteristics of a packet-based timing protocol are provided. A packet delay variation test sequence is applied to packet-based traffic as the packet-based traffic passes through a packet delay variation generator during transmission between nodes. Adaptive timing characteristics at a node that receives the packet-based traffic are evaluated in accordance with the packet delay variation test sequence.Type: ApplicationFiled: June 14, 2007Publication date: December 18, 2008Inventor: P. Stephan Bedrosian