Abstract: A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

Abstract: A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.

Abstract: A modulator comprises a polar generation stage that generates an amplitude and phase component of a modulation signal, a differentiator stage that generates a differentiated phase component by differentiating the phase component; and an event detection stage that detects a high bandwidth event by detecting the amplitude component and/or the differentiated phase component meeting an event criterion. An inversion stage generates a modified amplitude component by inverting the amplitude component in response to detecting the high bandwidth event. A phase offset stage generates a modified differentiated phase component by, in response to detecting the high bandwidth event, adding to the differentiated phase component a phase offset having a magnitude of 180° and a sign opposite to a sign of the differentiated phase component.

Abstract: A modulator (100) comprises a polar generation stage (120) arranged for generating an amplitude component and a phase component of a modulation signal, a differentiator stage (150) arranged for generating a differentiated phase component by differentiating the phase component; and an event detection stage (170) arranged for detecting a high bandwidth event by detecting at least one of the amplitude component and the differentiated phase component meeting an event criterion. An inversion stage (130) is arranged for generating a modified amplitude component by inverting the amplitude component in response to detecting the high bandwidth event. A phase offset stage (150) is arranged for generating a modified differentiated phase component by, in response to detecting the high bandwidth event, adding to the differentiated phase component a phase offset having a magnitude of 180 degrees and a sign opposite to a sign of the differentiated phase component.

Abstract: A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronisation stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.

Abstract: A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.

Abstract: A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.

Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.

Abstract: A resistive/residual Charge to Digital Timer (RCDT) provides efficient, accurate measurement of short time delay between two signals, by converting the time delay to current, and measuring the charge integrated by a capacitor over a duration. In one embodiment, in quantizing this charge (measured as voltage), a residual charge is maintained cycle-to-cycle. This allows for implementation of a Noise shaping Charge to Digital Timer (NCDT), providing improved resolution over a plurality of measurement cycles. The RCDT/NCDT is particularly (but not exclusively) well suited for phase error detection in a Digital Phase Locked Loop.

Abstract: A method and apparatus for controlling phase locked loop are provided. The apparatus includes a voltage controlled oscillator configured to generate an output signal with a frequency proportional to a control voltage fed into the oscillator. The apparatus also includes an analog loop filter connected to the oscillator and configured to form the control voltage for the oscillator, and a charge pump configured to generate a current pulse into the loop filter. The apparatus includes a phase-frequency detector operationally connected to the charge pump and configured to form waveforms, based on a reference signal and a feedback signal, the feedback signal being proportional to the output signal of the oscillator. The apparatus further includes a controller configured to modulate the feedback signal on the basis of the frequency or phase error of the output signal of the voltage controlled oscillator and the reference signal.

Abstract: The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.

Abstract: This invention describes a method for gain tuning of a voltage-controlled oscillator of a phase locked loop (PLL) of an electronic device using voltage measurements and a frequency iteration. The invention presents a method of minimizing integrated VCO gain variations. More specifically, the invention implementation is based on an analysis which includes changing the VCO frequency by iteration steps and optionally calculating said iteration steps and measuring a gain of said voltage controlled oscillator (VCO) at said frequencies changed by the iteration steps, wherein the analysis is based on a predetermined criterion. The present invention can be used in any radio architecture that requires limiting of the VCO gain variation and tuning its center frequency.

Abstract: This invention describes a method for simultaneous precise center frequency tuning and limiting a gain variation of a voltage controlled oscillator (VCO) of a phase locked loop (PLL) of an electronic device (e.g., a communication device, a mobile electronic device, a mobile phone, etc.). The invention utilizes frequency measurements and arithmetical optimizations. More specifically, the invention implementation is based on an analysis which includes measuring a frequency of a VCO and calculating a gain of the voltage controlled oscillator (VCO) using a predetermined criterion. The key element for implementing said analysis is a control and arithmetic block. The present invention can be used in any radio architecture that requires limiting of the VCO gain variation and tuning its center frequency.