Abstract: A method for data retrieval includes receiving a set of probability metrics. A set of probability metrics is received for each one of a plurality of read values, and each probability metric of the set of probability metrics corresponds to a statistical likelihood that the read value is representative of one of a number of symbols. The symbols define a set of allowed transitions between a number of states, and a series of successive allowed transitions between states define allowed paths between the states. The method further includes determining a survival path between the states. The survival path is based on an accumulation of probability metrics corresponding to the statistical likelihood that successive ones of the plurality of read values are representative of successive ones of the symbols defining each transition in the survival path. The method further includes decoding a symbol stream based on the survival path.

Abstract: A method for data retrieval includes receiving a set of probability metrics. A set of probability metrics is received for each one of a plurality of read values, and each probability metric of the set of probability metrics corresponds to a statistical likelihood that the read value is representative of one of a number of symbols. The symbols define a set of allowed transitions between a number of states, and a series of successive allowed transitions between states define allowed paths between the states. The method further includes determining a survival path between the states. The survival path is based on an accumulation of probability metrics corresponding to the statistical likelihood that successive ones of the plurality of read values are representative of successive ones of the symbols defining each transition in the survival path. The method further includes decoding a symbol stream based on the survival path.

Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

Abstract: A flash memory controller is configured to provide a first erase mode for erasing one or more groups of flash memory cells in a flash memory device using a plurality of erase pulses and a second erase mode for erasing the one or more groups of flash memory cells using a single erase pulse. The controller may receive a fast erase signal to erase the one or more groups of flash memory cells and, in response to the signal, switch operating parameters of the flash memory device from first parameters corresponding to the first erase mode to second parameters corresponding to the second erase mode, and instruct the flash memory device to perform an erase operation on the one or more groups of flash memory cells according to the second parameters. The controller may then verify that the erase operation was completed using the single erase pulse.

Abstract: A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter.

Abstract: A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter.

Abstract: A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of:shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs,encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, andinterleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.

Abstract: An on-chip self-test circuit for testing digital elements of a synchronous sampling data detection channel chip, such as a PRML channel of a hard disk drive, with digital pseudo samples representative of samples coming from an analog channel section, includes a sample generator generating idealized digital pseudo samples in accordance with a predetermined spectrum response, a digital noise generator generating digital noise values, a first combining circuit combining the idealized digital pseudo samples with the digital noise values to produce noisy pseudo samples, a bias injection circuit connected to the sample generator and adding a predetermined bias to the idealized digital pseudo samples to produce biased pseudo samples, and a second combining circuit for combining the noisy pseudo samples with the biased pseudo samples to put out biased noisy pseudo samples to test digital data processing and channel control elements of the channel chip.

Abstract: A new method for overlapping block read events in a disk drive having synchronously sampled data detection channels is presented. In particular, the new method is for overlapping read back processing by real-time and digital signal processing of first and second data blocks from a storage medium. The method includes steps of clocking real-time and digital signal processes by a clock synchronized to the first data block while the first data block is passing by a data transducer head, clocking the digital signal processes for the first data block by an asynchronous clock operating at a nominal data clocking rate after the first data block has passed by the data transducer head and before a clock has synchronized to the second data block following the first data block, and clocking real-time signal processes for the second data block and completing clocking of the digital processes for the first data block by a clock synchronized to the second data block passing by the data transducer head.

Abstract: Write precomposition optimization for a partial response maximum likelihood ("PRME") magnetic recording chapel adapted to a mass production environment. Optimal write precompensation may be determined by writing a tribit data pattern known to produce worst case nonlinear transition shift ("NLTS") onto a magnetic recording medium; reading back the recorded data pattern; and calculating the mean-squared error ("MSE") for one or more of the equalized data sample levels associated with the PRML channel to be optimized. The writing and reading back process is repeated with varying amounts of precompensation applied to the written pattern. The optimal amount of write precompensation is determined eider by minimizing the MSE for a selected sample level or by minimizing MSE between the middle and the upper or lower of the ternary PRML sample levels.

Abstract: A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.

Abstract: Write precompensation optimization for a partial response maximum likelihood ("PRML") magnetic recording channel adapted to a mass production environment. Optimal write precompensation may be determined by writing a tribit data pattern known to produce worst case nonlinear transition shift ("NLTS") onto a magnetic recording medium; reading back the recorded data pattern; and calculating the mean-squared error ("MSE") for one or more of the equalized data sample levels associated with the PRML channel to be optimized. The writing and reading back process is repeated with varying amounts of precompensation applied to the written pattern. The optimal amount of write precompensation is determined either by minimizing the MSE for a selected sample level or by minimizing MSE between the middle and the upper or lower of the ternary PRML sample levels.

Abstract: An apparatus and method for removing direct current (DC) offset from a received analog signal having DC offset introduced during analog signal processing. The preferred circuit has a DC offset control loop that is enabled and operates in real-time during the reading of a sinusoidal preamble pattern. The control loop rapidly cancels DC offset by subtracting a learned correction value from the incoming analog signal being processed. Before end of preamble playback the loop is disabled and the learned correction value held during data read times. The DC offset control loop is not dependent upon correct sampling phase decisions in order to properly determine the DC offset correction value, and it is orthogonal with respect to the gain and timing control loops in a sampled data system thereby minimizing cross-talk or other interference between the several control loops.

Abstract: A 10-tap finite impulse response (FIR) digital filter is provided in a partial response signaling and maximum-likelihood (PRML) data channel. A plurality of partial sums of predetermined tap weights are stored in a palette random access memory (RAM). A fixed qualifier value is received and used together with selected ones of the stored partial sums for calculating a predetermined tap weight. Predetermined filter coefficients are calculated and stored in a filter RAM using the calculated predetermined tap weight and predefined ones of the stored partial sums.

Abstract: A method and apparatus are provided for controlling a digital filter function included in a data path within gain and timing control loops of a PRML magnetic recording channel. The digital filter function is removed from the data path during an acquisition mode and the digital filter function is restored to the data path during a tracking mode. A predetermined gain and a quantized delay at a synchronization frequency are provided when switching from acquisition mode to tracking mode. A unity gain and a delay of an integer number of sample periods are provided at a synchronization frequency when switching from acquisition mode to tracking mode.