Patents by Inventor Pablo Cruz

Pablo Cruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230356982
    Abstract: A control unit is used to perform a method for installing an elevator system including the steps of: using an at least partially installed traveling body as a movable working platform borne by traction means and having an electronic safety brake; creating an operating state of the safety brake using the control unit to control the safety brake, the control unit having an input from a safety sensor, a processing unit and a signal output connected to the safety brake; generating a control signal by the processing unit at the signal output, wherein the control signal controls the safety brake; detecting an unsafe operating state by the safety sensor; controlling the signal output due to a detection of an unsafe operating state by the processing unit so that the safety brake is triggered; and removing the control unit when the installation of the elevator system is complete.
    Type: Application
    Filed: September 3, 2021
    Publication date: November 9, 2023
    Inventors: Pablo Cruz, Astrid Sonnenmoser, Adrian Steiner
  • Publication number: 20220098622
    Abstract: The present invention provides for a cyclopropane compound having the following chemical formula: wherein ? is —H or —COOR, wherein R is —H or an alkyl group, such as —CH3, —CH2CH3, —(CH2)2—CH3, —(CH2)3—CH3, or —C(CH3)3; ? is each independently wherein at least one ? is and, n is an integer from 3 to 11. A fuel composition comprising the cyclopropane compound thereof and a fuel additive. The present invention also provides for a system or genetically modified host cell capable of producing the cyclopropane compound, and a method for producing the cyclopropane compound.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 31, 2022
    Inventors: Pablo Cruz-Morales, Kevin Yin, Robert Bertrand, Ethan Oksen, Aidan Cowan, Yuzhong Liu, Eric Sundstrom, Jay D. Keasling
  • Patent number: 10931290
    Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 23, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
  • Patent number: 10727848
    Abstract: A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 28, 2020
    Assignee: Analog Devices Global
    Inventors: Pablo Cruz Dato, Declan M. Dalton, Patrick G. Crowley
  • Patent number: 10509104
    Abstract: Apparatus and methods for synchronization of multiple semiconductor dies are provided herein. In certain implementations, a reference clock signal is distributed to two or more semiconductor dies that each include at least one data converter. The two or more dies include a master die that generates a data converter synchronization signal, and at least one slave die that processes the data converter synchronization signal to align timing of data conversion operations across the dies, for instance, to obtain a high degree of timing coherence for digital sampling. In certain implementations, the dies correspond to radar chips of a radar system, and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. Additionally, the master radar chip generates a ramp synchronization signal to synchronize transmission sequencing across the radar chips and/or to provide phase alignment of ADC clock signals.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Pablo Cruz Dato
  • Publication number: 20190305785
    Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
  • Patent number: 10414796
    Abstract: The present invention describes a new peptide aldehyde produced naturally by Streptomyces lividans 66, which we have called livipeptin. Using genome mining of natural products, we predicted that SLI0883-5 genes encode an unprecedented biosynthetic system, unusually small (4.6 Kbp), which produces an acylated peptide aldehyde. Because of the chemical characteristics of the predicted compound, we postulated its anti-proteolytic activity, which we confirmed by identifying and purifying this compound through metabolic profiles of HPLC and MS of the mutated strain lacking these three genes and the wild strain. To this objective, we identified the conditions wherein these genes are strongly expressed. The livipeptin was purified and its inhibitory activity on the proteolytic activity of selected proteases was demonstrated in vitro. The design of an expression cassette for its heterologous expression is also described plus its use for heterologous protein production.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: September 17, 2019
    Assignee: Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional
    Inventors: Pablo Cruz Morales, Francisco Barona Gómez, Hilda Eréndira Ramos Aboites
  • Patent number: 10340926
    Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
  • Patent number: 10295580
    Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 21, 2019
    Assignee: Analog Devices Global
    Inventors: Vamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
  • Publication number: 20180265545
    Abstract: The present invention describes a new peptide aldehyde produced naturally by Streptomyces lividans 66, which we have called livipeptin. Using genome mining of natural products, we predicted that SLl0883-5 genes encode an unprecedented biosynthetic system, unusually small (4.6 Kbp), which produces an acylated peptide aldehyde. Because of the chemical characteristics of the predicted compound, we postulated its anti-proteolytic activity, which we confirmed by identifying and purifying this compound through metabolic profiles of HPLC and MS of the mutated strain lacking these three genes and the wild strain. To this objective, we identified the conditions wherein these genes are strongly expressed. The livipeptin was purified and its inhibitory activity on the proteolytic activity of selected proteases was demonstrated in vitro. The design of an expression cassette for its heterologous expression is also described plus its use for heterologous protein production.
    Type: Application
    Filed: December 14, 2015
    Publication date: September 20, 2018
    Applicant: Centro de Investigación y de Estudios Avanzados del Instituto Politécnico Nacional
    Inventors: Pablo CRUZ MORALES, Francisco BARONA GÓMEZ, Hilda Eréndira RAMOS ABOITES
  • Publication number: 20180097522
    Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 5, 2018
    Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
  • Publication number: 20180095119
    Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 5, 2018
    Inventors: Vamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
  • Publication number: 20170012631
    Abstract: A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 12, 2017
    Inventors: Pablo Cruz Dato, Declan D. Dalton, Patrick G. Crowley
  • Patent number: 7444732
    Abstract: A device and method for installing guide rails in an elevator shaft includes a common support to line up the guide rails as an assembly. At least one coupling element per guide rail is provided in order to fasten the guide rails to the support. The common support is designed so that the guide rails can be fastened one after the other to the common support.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 4, 2008
    Assignee: Inventio AG
    Inventors: Pablo Cruz, Ernst Ach
  • Patent number: 7367430
    Abstract: A wedge-ribbed belt supports an elevator car in a cantilevered mode and engages a drive pulley of a drive mounted at the head of an elevator shaft. The belt has a running surface facing the drive pulley with a plurality of ribs and grooves extending in parallel in a longitudinal direction of the belt. The ribs and grooves can be triangular-shaped or trapezium-shaped in cross section. A plane of the drive pulley is arranged vertically and at right angles to a car wall at a counterweight side of the elevator car.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: May 6, 2008
    Assignee: Inventio AG
    Inventors: Ernst Friedrich Ach, Pablo Cruz Bello
  • Publication number: 20070181384
    Abstract: A method of mounting an elevator installation includes providing an elevator car in the lower shaft region, introducing a support belt into the elevator shaft and guiding the belt around the car deflecting rollers arranged at the bottom at the elevator car. The remaining portions of the belt are stored in the region of a work platform of the elevator car. The elevator car is raised into an upper shaft region and the first end of the belt is fastened to a first connecting point. The second end of the belt is led around a traction pulley and a loop, between the traction pulley and the second end, is let down to the lower shaft region and a counterweight deflecting means inclusive of a counterweight is suspended in the loop. The second end of the support belt then is attached at the second connecting point.
    Type: Application
    Filed: October 4, 2006
    Publication date: August 9, 2007
    Applicant: INVENTIO AG
    Inventor: Pablo Cruz
  • Publication number: 20060259171
    Abstract: A delivery unit is created using a corresponding computer-assisted method of providing components of a transport system. The method includes the steps of: providing a parts list; providing associated assembly information; and packing up the components, wherein the components are packed up by packing material with consideration of the assembly information to form delivery units.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 16, 2006
    Inventor: Pablo Cruz
  • Publication number: 20060243539
    Abstract: A device and method for installing guide rails in an elevator shaft includes a common support to line up the guide rails as an assembly. At least one coupling element per guide rail is provided in order to fasten the guide rails to the support. The common support is designed so that the guide rails can be fastened one after the other to the common support.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 2, 2006
    Applicant: Inventio AG
    Inventors: Pablo Cruz, Ernst Ach