Patents by Inventor Pablo De Lara Guarch

Pablo De Lara Guarch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113863
    Abstract: Methods and apparatus relating to an efficient implementation of ZUC authentication are described. In one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. The tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: March 31, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Pablo De Lara Guarch, Tomasz Kantecki, Krystian Matusiewicz, Wajdi Feghali, Vinodh Gopal, James D. Guilford
  • Publication number: 20240048543
    Abstract: An apparatus includes an interface to memory, and a processor to execute one or more instructions. The instructions cause the processor to receive, via an application programming interface (API), a plurality of packets, respective packets of the plurality of packets comprising a respective header and a respective payload. Further, the instructions cause the processor to determine, by a QUIC protocol stack, to encrypt the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the payloads of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 8, 2024
    Applicant: Intel Corporation
    Inventors: Ping Yu, Tomasz Kantecki, Chao Dou, Pablo De Lara Guarch, Brian Will
  • Patent number: 11500825
    Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 15, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ren Wang, Bruce Richardson, Tsung-Yuan Tai, Yipeng Wang, Pablo De Lara Guarch
  • Publication number: 20220224511
    Abstract: Examples described herein relate to executing, on at least one processor, at least one Advanced Encryption Standard (AES) instruction, having an operation code (opcode), on operands, wherein execution of the at least one AES instruction generates an S1 box and/or S2 box of initialization and keystream generation for a SNOW3 cipher operation.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Kamila LIPINSKA, Tomasz KANTECKI, Marcel CORNU, Pablo DE LARA GUARCH, Stephen MCINTYRE, Krystian MATUSIEWICZ, James GUILFORD, Vinodh GOPAL, Wajdi FEGHALI
  • Publication number: 20190280991
    Abstract: At a network interface, received packets are classified according to priority level or traffic class. Based on an assigned priority level, a received packet can be allocated to use a descriptor queue associated with the assigned priority level. The descriptor queue can have an associated buffer region in which portions of received packets are stored. The length of the descriptor queue can be dependent on the priority level such that a highest priority descriptor queue can be longer than a lowest priority descriptor queue. The size of the buffer can be dependent on the priority level such that a highest priority level can be assigned a separate buffer space of different size than that assigned to a lower priority level. A polling rate for a descriptor queue can be configured based on a priority level such that a highest priority level descriptor queue can be polled more frequently than a polling of a lower priority level descriptor queue.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 12, 2019
    Inventors: Jasvinder SINGH, Pablo DE LARA GUARCH, Kevin LAATZ, CIARA POWER, Greg CURRAN, John J. BROWNE
  • Publication number: 20190042602
    Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 7, 2019
    Inventors: Ren Wang, Bruce Richardson, Tsung-Yuan Tai, Yipeng Wang, Pablo De Lara Guarch