Patents by Inventor Pablo Jarillo-Herrero

Pablo Jarillo-Herrero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11837873
    Abstract: Rectification is a process that converts electromagnetic fields into direct current (DC). Such a process underlies a wide range of technologies, including wireless communication, wireless charging, energy harvesting, and infrared detection. Existing rectifiers are mostly based on semiconductor diodes, with limited applicability to small voltages or high frequency inputs. Here, we present an alternative approach to current rectification that uses the electronic properties of quantum crystals without semiconductor junctions. We identify a new mechanism for rectification from skew scattering due to the chirality of itinerant electrons in time-reversal-invariant but inversion-breaking materials. Our calculations reveal large, tunable rectification effects in graphene multilayers and transition metal dichalcogenides. These effects can be used in high-frequency rectifiers by rational material design and quantum wavefunction engineering.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: December 5, 2023
    Assignee: Massachusetts Institute of Technology
    Inventors: Hiroki Isobe, Qiong Ma, Liang Fu, Nuh Gedik, Suyang Xu, Pablo Jarillo-Herrero
  • Patent number: 11393976
    Abstract: An ultrathin, carbon-based memristor with a moiré superlattice potential shows prominent ferroelectric resistance switching. The memristor includes a bilayer material, such as Bernal-stacked bilayer graphene, encapsulated between two layers of a layered material, such as hexagonal boron nitride. At least one of the encapsulating layers is rotationally aligned with the bilayer to create the moiré superlattice potential. The memristor exhibits ultrafast and robust resistance switching between multiple resistance states at high temperatures. The memristor, which may be volatile or nonvolatile, may be suitable for neuromorphic computing.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: July 19, 2022
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Pablo Jarillo-Herrero, Qiong Ma, Nuh Gedik, Suyang Xu, Zhiren Zheng
  • Publication number: 20210384762
    Abstract: Rectification is a process that converts electromagnetic fields into direct current (DC). Such a process underlies a wide range of technologies, including wireless communication, wireless charging, energy harvesting, and infrared detection. Existing rectifiers are mostly based on semiconductor diodes, with limited applicability to small voltages or high frequency inputs. Here, we present an alternative approach to current rectification that uses the electronic properties of quantum crystals without semiconductor junctions. We identify a new mechanism for rectification from skew scattering due to the chirality of itinerant electrons in time-reversal-invariant but inversion-breaking materials. Our calculations reveal large, tunable rectification effects in graphene multilayers and transition metal dichalcogenides. These effects can be used in high-frequency rectifiers by rational material design and quantum wavefunction engineering.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 9, 2021
    Applicant: Massachusetts Institute of Technology
    Inventors: Hiroki Isobe, Qiong MA, Liang FU, Nuh GEDIK, Suyang XU, Pablo Jarillo-Herrero
  • Publication number: 20210217952
    Abstract: An ultrathin, carbon-based memristor with a moiré superlattice potential shows prominent ferroelectric resistance switching. The memristor includes a bilayer material, such as Bernal-stacked bilayer graphene, encapsulated between two layers of a layered material, such as hexagonal boron nitride. At least one of the encapsulating layers is rotationally aligned with the bilayer to create the moiré superlattice potential. The memristor exhibits ultrafast and robust resistance switching between multiple resistance states at high temperatures. The memristor, which may be volatile or nonvolatile, may be suitable for neuromorphic computing.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 15, 2021
    Inventors: Pablo Jarillo-Herrero, Qiong MA, Nuh GEDIK, Suyang XU, Zhiren ZHENG
  • Patent number: 8659009
    Abstract: A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: February 25, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Barbaros Ozyilmaz, Dmitri Efetov, Pablo Jarillo-Herrero, Philip Kim
  • Publication number: 20090140801
    Abstract: A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 4, 2009
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Barbaros Ozyilmaz, Dmitri Efetov, Pablo Jarillo-Herrero, Melinda Y. Han, Philip Kim