Abstract: A distributed communication center configured to handle a plurality of communications includes a user zone, a web zone, and a network zone. The user zone includes a plurality of remote terminals that enable communication center personnel and end users to remotely interface with the distributed communication center through the web zone. The web zone includes one or more web servers configured and one or more mail servers to interface the remote terminals in the user zone with the network zone. The network zone includes one or more telephony servers and one or more application servers.

Abstract: A distributed communication center configured to handle a plurality of communications includes a user zone, a web zone, and a network zone. The user zone includes a plurality of remote terminals that enable communication center personnel and end users to remotely interface with the distributed communication center through the web zone. The web zone includes one or more web servers configured and one or more mail servers to interface the remote terminals in the user zone with the network zone. The network zone includes one or more telephony servers and one or more application servers.

Abstract: A distributed communication center configured to handle a plurality of communications includes a user zone, a web zone, and a network zone. The user zone includes a plurality of remote terminals that enable communication center personnel and end users to remotely interface with the distributed communication center through the web zone. The web zone includes one or more web servers configured and one or more mail servers to interface the remote terminals in the user zone with the network zone. The network zone includes one or more telephony servers and one or more application servers.

Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.

Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.

Abstract: A system and method for controlling output buffer drive enable signals on a parallel terminated bus is described. The method includes transferring data between a first agent and a second agent, tracking outstanding data requests from the first agent with at least one synchronous counter, tracking outstanding data replies from the second agent with a source synchronous counter, and driving a signal on the parallel terminated bus when the synchronous and source synchronous counters match.

Abstract: A system and method for enhancing the performance of a parallel terminated bus. An implementation includes storing a minimum spacing for each transaction type in a memory, monitoring data transactions, performing a latch back operation if required, and executing a subsequent transaction following a prior transaction using a minimum spacing if the latch back operation does not occur.

Abstract: An integrated circuit for measuring internal clock skew is provided. The integrated circuit includes a first controlled delay module, which is operable to receive one of a sampling clock signal and a sampled clock signal. The integrated circuit further includes a first flip-flop having a first input coupled to the first controlled delay module and a second input coupled to one of the sampling clock signal and said sampled clock signal. The first flip-flop is operable to generate an output based on skew between the sampled clock signal and the sampling clock signal.

Abstract: A method for ensuring proper strobe pre and post driving between a first data transfer and a second data transfer in a microprocessor system. The method includes generating a first strobe signal and a second strobe signal, pre-driving one of said first and second strobe signals before the first data transfer, post driving said pre-driven signal, determining which of said first and second strobe signals will be post driven, and pre-driving one of said first and second strobe signals before the second data transfer.

Abstract: A circuit to detect predetermined power supply levels so that sufficient power is provided for an integrated circuit to function properly and drive a bus. A first circuit indicates whether a first voltage has reached a first level, a second circuit indicates whether a second voltage has reached a second level, and a third circuit causes the second circuit to operate in a low power mode when the second voltage has reached a predetermined level. The first voltage is provided by an I/O power supply and the second voltage is provided by a core power supply.

Abstract: A method and apparatus for detecting and in some cases recovering from errors in a source synchronous bus. One embodiment of a disclosed apparatus includes a plurality of strobe inputs to receive a plurality of strobe signals. A plurality of data inputs receive a plurality of data signals transmitted in a source synchronous manner in conjunction with the strobe signals. Bus control logic produces an externally visible indication that an error has occurred if a glitch on one or more of the plurality of strobe signals is detected.

Abstract: A system and method for enhancing the performance of a parallel terminated bus. An implementation includes storing a minimum spacing for each transaction type in a memory, monitoring data transactions, performing a latch back operation if required, and executing a subsequent transaction following a prior transaction using a minimum spacing if the latch back operation does not occur.

Abstract: A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.

Abstract: A method and apparatus are provided for increasing the density and performance of a Content Addressable Memory (CAM). According to one embodiment, the CAM includes a comparison circuit, an enable circuit, and a bias circuit. The comparison circuit compares a stored bit to an input bit and outputs an inverted result of the comparison. The enable circuit receives as inputs the inverted result of the comparison and an enable input and produces an enabled comparison result. The bias circuit receives the enabled comparison result as its only input and discharges a pull-down line based upon the enabled comparison result.