Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and comprising a main processor for implementing functionality of the management controller and a co-processor communicatively coupled to the host system processor and configured to implement a proxy to the host system to enable the host system to access devices managed by the management controller.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of a plurality of devices of the information handling system, and further configured to, during a powering on of the host system randomly select a subset of one or more devices of the plurality of devices for partial validation of firmware of the plurality of devices, randomly select a plurality of offsets associated with the one or more devices for partial verification of the firmware, and perform verification of the one or more devices at the plurality of offsets.

Abstract: An information handling system includes an air mover and a thermal manager. The thermal manager identifies an air mover identification event for the air mover; in response to identifying the air mover identification event: places the air mover in a type identification state, and while the air mover is in the type identification state, identifies a type of the air mover; and, after identifying the type of the air mover, places the air mover in an active state based on the type of the air mover.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of a plurality of devices of the information handling system, and further configured to, during a powering on of the host system randomly select a subset of one or more devices of the plurality of devices for partial validation of firmware of the plurality of devices, randomly select a plurality of offsets associated with the one or more devices for partial verification of the firmware, and perform verification of the one or more devices at the plurality of offsets.

Abstract: An information handling system may include a host system comprising a processor and a management controller comprising a main processor and a trusted integrated processor configured to perform secured boot services and run-time security functions of the management controller. The information handling system may also include a legacy communications bus interfaced between the host system and the main processor and a secure communications bus interfaced between the host system and the main processor. The trusted integrated processor is further configured to implement a secure attestation channel to the host system via the secure communications bus in order to provide access by the host system to security services owned by the management controller.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and comprising a main processor for implementing functionality of the management controller and a co-processor communicatively coupled to the host system processor and configured to implement a proxy to the host system to enable the host system to access devices managed by the management controller.

Abstract: An information handling system includes an air mover and a thermal manager. The thermal manager identifies an air mover identification event for the air mover; in response to identifying the air mover identification event: places the air mover in a type identification state, and while the air mover is in the type identification state, identifies a type of the air mover; and, after identifying the type of the air mover, places the air mover in an active state based on the type of the air mover.

Abstract: Embodiments provide methods and systems for detecting rogue endpoints on a device management bus. A communications controller configured as a bus owner initiates discovery of managed devices coupled to the bus and generate a unique identifier for each managed device. The communications controller transmits a bus configuration message to the managed devices, including the respective unique identifiers. The managed devices are configured as bus endpoints based on the bus configuration message. The managed devices also capture the bus address of the communications controller from the received bus configuration message. Messages received by a managed device are authenticated as originating from the communications controller if the messages include the unique identifier provided to that managed device. The messages may be further authenticated by comparing the bus address of the message sender against the captured bus address of the communications controller.

Abstract: An information handling system includes a host processing complex with a memory, and a baseboard management controller (BMC) with a processor and a video capture and difference engine (VCDE). The processor receives a memory compare command. The memory compare command includes a first pointer to a first block of the memory, a second pointer to a second block of the memory, and a memory block size. The processor further determines whether the memory block size is greater than a threshold, and forwards the memory compare command to the VCDE when the memory block size is greater than the threshold. The VCDE compares contents of the first block to contents of the second block in response to receiving the memory compare command.

Abstract: An apparatus executes a boot operation, and determines a planar type associated with a motherboard. The apparatus queries an electronic database for the planar type associated with the motherboard, and identifies a branding identity that is electronically associated with the planar type.

Abstract: Embodiments provide methods and systems for detecting rogue endpoints on a device management bus. A communications controller configured as a bus owner initiates discovery of managed devices coupled to the bus and generate a unique identifier for each managed device. The communications controller transmits a bus configuration message to the managed devices, including the respective unique identifiers. The managed devices are configured as bus endpoints based on the bus configuration message. The managed devices also capture the bus address of the communications controller from the received bus configuration message. Messages received by a managed device are authenticated as originating from the communications controller if the messages include the unique identifier provided to that managed device. The messages may be further authenticated by comparing the bus address of the message sender against the captured bus address of the communications controller.

Abstract: Sideband device management bus messages are filtered using software operations in order to minimize dropped messages and to maintain the bus in an operable state. Redundant sideband device management buses are utilized in order to provide fail-over transmission of messages in scenarios where one of the buses becomes inoperable. Multi-packet messages are transmitted to managed devices via the sideband bus connections. If an inoperable state is detected in a sideband bus connection during transmission of a multi-packet message, the portion of the multi-packet message not received by the managed device is transmitted via a redundant sideband bus connection with the managed device. Software filtering of bus transactions utilizes a circular DMA buffer for storing all incoming transactions. Transactions of interest are copied to buffers associated with specific endpoints for processing.

Abstract: A baseboard management controller (BMC) includes a plurality of device I2C interfaces. Each device I2C interfaces provides a device I2C bus that is ported externally to the BMC. The BMC further includes a plurality of device buffer/switch circuits. Each device buffer/switch circuit is connected to a respective device I2C bus, and is configured to selectably connect to the respective I2C bus in a high-impedance mode, an open-drain mode, and a FET switch mode. The BMC further includes a multiplexor/driver circuit that has a multiplexor I2C interface that provides a multiplexor I2C bus that is ported externally to the BMC. The multiplexor/driver circuit is coupled to each device I2C bus via the respective buffer/switch circuit, and is configured to selectively couple one of the device I2C busses to the multiplexor I2C bus, and to select one of the high-impedance mode, the open-drain mode, or the FET switch mode for the selected buffer/switch circuit.

Abstract: An information handling system includes a host processing complex with a memory, and a baseboard management controller (BMC) with a processor and a video capture and difference engine (VCDE). The processor receives a memory compare command. The memory compare command includes a first pointer to a first block of the memory, a second pointer to a second block of the memory, and a memory block size. The processor further determines whether the memory block size is greater than a threshold, and forwards the memory compare command to the VCDE when the memory block size is greater than the threshold. The VCDE compares contents of the first block to contents of the second block in response to receiving the memory compare command.

Abstract: An apparatus executes a boot operation, and determines a planar type associated with a motherboard. The apparatus queries an electronic database for the planar type associated with the motherboard, and identifies a branding identity that is electronically associated with the planar type.

Abstract: A baseboard management controller (BMC) includes a plurality of device I2C interfaces. Each device I2C interfaces provides a device I2C bus that is ported externally to the BMC. The BMC further includes a plurality of device buffer/switch circuits. Each device buffer/switch circuit is connected to a respective device I2C bus, and is configured to selectably connect to the respective I2C bus in a high-impedance mode, an open-drain mode, and a FET switch mode. The BMC further includes a multiplexor/driver circuit that has a multiplexor I2C interface that provides a multiplexor I2C bus that is ported externally to the BMC. The multiplexor/driver circuit is coupled to each device I2C bus via the respective buffer/switch circuit, and is configured to selectively couple one of the device I2C busses to the multiplexor I2C bus, and to select one of the high-impedance mode, the open-drain mode, or the FET switch mode for the selected buffer/switch circuit.