Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.

Abstract: A PVT detection circuit including: first and second transistors of a first conduction type each having its control node coupled to a control line, the first and second transistors being configured such that the variations in their threshold voltages as a function of temperature and/or process are different from each other; and an amplifier coupled to a second main conducting node of each of the first and second transistors and configured to amplify a difference in the currents conducted by the first and second transistors in order to generate an output signal.

Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.

Abstract: A PVT detection circuit including: first and second transistors of a first conduction type each having its control node coupled to a control line, the first and second transistors being configured such that the variations in their threshold voltages as a function of temperature and/or process are different from each other; and an amplifier coupled to a second main conducting node of each of the first and second transistors and configured to amplify a difference in the currents conducted by the first and second transistors in order to generate an output signal.