Abstract: Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.

Abstract: Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.

Abstract: Various systems and methods for delaying one signal in relation to another are disclosed. As one example, a delay lock loop circuit is discussed that includes at least a first delay stage and a second delay stage, each including a plurality of selectable delay elements. The delay stages are configured such that a gated reference signal drives an input of the first delay stage, and a first output from the first delay stage drives an input of the second delay stage. The circuits further include a unified selector register that is associated with both the first delay stage and the second delay stage. A value maintained in the unified selector register determines a number of the selectable delay elements utilized in the first delay stage and a number of the selectable delay elements utilized in the second delay stage. In operation, modification of the value maintained in the unified selector register is synchronized to the reference signal.

Abstract: Various embodiments of the present invention provide delay lock loop circuits. Such delay lock loop circuits include two or more delay stages that each include a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, and the first delay stage provides a first output. The first output drives an input of the second delay stage, and the second delay stage provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. Modification of the value maintained in the first selector register is synchronized to the first output. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage.

Abstract: Various systems and methods for delaying a signal relative to another signal are disclosed. As one example, a delay lock loop circuit is disclosed that includes at least two delay stages. Each of the aforementioned delay stages include a plurality of selectable delay elements. Such selectable delay elements may be, but are not limited to, a plurality of single input buffers, and a plurality of multiple input logic gates. Further, a first of the delay stages is selectably driven by one of a first signal and a reference signal, and the stage provides a first stage output. A second of the delay stages is selectably driven by one of a second signal and the first stage output, and the stage provides a second stage output. The circuit further includes a mode signal that has at least two states.