Patents by Inventor Padmaja NAGAIAH

Padmaja NAGAIAH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286967
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Jing WAN, Jer-Hueih(James) CHEN, Cuiqin XU, Padmaja NAGAIAH
  • Patent number: 10020383
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jing Wan, Jer-Hueih(James) Chen, Cuiqin Xu, Padmaja Nagaiah
  • Publication number: 20160343607
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventors: Jing WAN, Jer-Hueih(James) CHEN, Cuiqin XU, Padmaja NAGAIAH
  • Patent number: 9209258
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
  • Publication number: 20150249136
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Feng ZHOU, Tien-Ying LUO, Haiting WANG, Padmaja NAGAIAH, Jean-Baptiste LALOE, Isabelle Pauline FERAIN, Yong Meng LEE