Abstract: A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.

Abstract: A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.