Patents by Inventor Padmanabh Gharpure

Padmanabh Gharpure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9209675
    Abstract: A device comprises a first power cell, a second power cell, a power factor correction module, a boost inductor switch circuit, and an output. The first and second power cells are configured to provide first and second currents in response to an input voltage. The power factor correction module is configured to continuously activate and deactivate the first and second power cells based on an input current level, on the input voltage, and on an output voltage. The boost inductor switch circuit is configured to disable the first power cell in response to the input current level being below a predetermined level. The output is configured to provide the output voltage based on the first and second currents when the input current level is above the predetermined level, and to provide the output voltage based on the second current when the input current level is below the predetermined level.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: December 8, 2015
    Assignee: Dell Products, LP
    Inventors: Lucian Popescu, Padmanabh Gharpure
  • Patent number: 8432713
    Abstract: A device comprises a first power cell, a second power cell, a power factor correction module, a boost inductor switch circuit, and an output. The first and second power cells are configured to provide first and second currents in response to an input voltage. The power factor correction module is configured to continuously activate and deactivate the first and second power cells based on an input current level, on the input voltage, and on an output voltage. The boost inductor switch circuit is configured to disable the first power cell in response to the input current level being below a predetermined level. The output is configured to provide the output voltage based on the first and second currents when the input current level is above the predetermined level, and to provide the output voltage based on the second current when the input current level is below the predetermined level.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: April 30, 2013
    Assignee: Dell Products, LP
    Inventors: Lucian Popescu, Padmanabh Gharpure
  • Patent number: 7796405
    Abstract: A device including a full bridge, a half bridge, a first inductor, and a second inductor. The full bridge has a first pair of transistors being activated when a load applied to the device is above a predetermined level and deactivated when the load applied to the device is below the predetermined level, and a second pair of transistors being continuously activated. The half bridge has a third pair of transistors that are activated when the load applied to the device is below the predetermined level and deactivated when the load applied to the device is above the predetermined level. The first and second inductors are connected between the outputs of the full and half bridges are adapted to cooperate with each other to provide a zero voltage switching of the device at a light load. The first and third pairs of transistors are activated at different times.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: September 14, 2010
    Assignee: Dell Products, LP
    Inventors: Lucian Popescu, Padmanabh Gharpure
  • Publication number: 20090295347
    Abstract: A device comprises a first power cell, a second power cell, a power factor correction module, a boost inductor switch circuit, and an output. The first and second power cells are configured to provide first and second currents in response to an input voltage. The power factor correction module is configured to continuously activate and deactivate the first and second power cells based on an input current level, on the input voltage, and on an output voltage. The boost inductor switch circuit is configured to disable the first power cell in response to the input current level being below a predetermined level. The output is configured to provide the output voltage based on the first and second currents when the input current level is above the predetermined level, and to provide the output voltage based on the second current when the input current level is below the predetermined level.
    Type: Application
    Filed: June 2, 2008
    Publication date: December 3, 2009
    Applicant: DELL PRODUCTS, LP
    Inventors: Lucian Popescu, Padmanabh Gharpure
  • Publication number: 20090251927
    Abstract: A device including a full bridge, a half bridge, a first inductor, and a second inductor. The full bridge has a first pair of transistors being activated when a load applied to the device is above a predetermined level and deactivated when the load applied to the device is below the predetermined level, and a second pair of transistors being continuously activated. The half bridge has a third pair of transistors that are activated when the load applied to the device is below the predetermined level and deactivated when the load applied to the device is above the predetermined level. The first and second inductors are connected between the outputs of the full and half bridges are adapted to cooperate with each other to provide a zero voltage switching of the device at a light load. The first and third pairs of transistors are activated at different times.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: DELL PRODUCTS, LP
    Inventors: Lucian Popescu, Padmanabh Gharpure