Patents by Inventor Padmanabha Venkitakrishnan

Padmanabha Venkitakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060190552
    Abstract: A data retention system is described that has a plurality of access protocols. The system comprises a memory store accessible through a virtual address space, a controller communicatively coupled to the memory store, and an interface. The controller is adapted to implement a memory access protocol for accessing at least a first portion of the virtual address space and a secondary storage protocol for accessing at least a second portion of the virtual address space. The interface is communicatively coupled to the controller, and is able to be communicatively coupled to a communications link.
    Type: Application
    Filed: February 24, 2005
    Publication date: August 24, 2006
    Inventors: Richard Henze, Padmanabha Venkitakrishnan, Scott Marovich, Pankaj Mehra, Samuel Fineberg
  • Patent number: 7003441
    Abstract: In one embodiment, for an electronic architecture with a functional constitution performing a number of functions characterized by separate stages performing subfunctions, a method of deriving a benchmark program for estimating the maximum power consumption by modeling a functional model of the architecture, compiling the benchmark program into a corresponding instruction stream, valuating power weights for each stage of each function of each constituent, inserting the power weights, running the model in a maximum power consumption mode, and summarizing power consumption. In one embodiment, the benchmark program is applied by specifying a design analysis to be performed, selecting a function, designating a stages performing that function, removing a set of instruction set architecture instructions corresponding the designated stage, emulating the constituent subfunction corresponding to the stages designated stage, and summarizing. In one embodiment, the model is written in SystemC.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: February 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Padmanabha Venkitakrishnan
  • Patent number: 6874014
    Abstract: Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen E. Richardson, Gary Vondran, Stuart Siu, Paul Keltcher, Shankar Venkataraman, Padmanabha Venkitakrishnan, Joseph Ku
  • Publication number: 20030037270
    Abstract: In one embodiment, for an electronic architecture with a functional constitution performing a number of functions characterized by separate stages performing subfunctions, a method of deriving a benchmark program for estimating the maximum power consumption by modeling a functional model of the architecture, compiling the benchmark program into a corresponding instruction stream, valuating power weights for each stage of each function of each constituent, inserting the power weights, running the model in a maximum power consumption mode, and summarizing power consumption. In one embodiment, the benchmark program is applied by specifying a design analysis to be performed, selecting a function, designating a stages performing that function, removing a set of instruction set architecture instructions corresponding the designated stage, emulating the constituent subfunction corresponding to the stages designated stage, and summarizing. In one embodiment, the model is written in SystemC.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 20, 2003
    Inventor: Padmanabha Venkitakrishnan
  • Patent number: 6513145
    Abstract: In one embodiment, the present invention provides a method for estimating the maximum power consumed in a microprocessor or other architecture, at an architectural level, prior to implementation. A functional model represents the architecture at a high level of abstraction. In one embodiment, the model is written in SystemC. In one embodiment, power consumption is expressed power weights, derived by reference to architecture technology. In one embodiment, a method of estimating power consumption prior to implementation operates by modeling a benchmark, compiling it into an instruction stream, assigning power weights for each stage of each architectural function, running the model in a maximum power consumption mode, and summarizing the resulting power consumption. In one embodiment, a PERL script compiler is used. In one embodiment, the power weights are calculated corresponding to the characteristic architecture technology. In one embodiment, a power virus program runs the model in the maximum power mode.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: January 28, 2003
    Assignee: Hewlett-Packard Company
    Inventor: Padmanabha Venkitakrishnan