Patents by Inventor Padmapani C. Nallan

Padmapani C. Nallan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7320942
    Abstract: A method for removal of metallic residue from a substrate after a plasma etch process in a semiconductor substrate processing system by cleaning the substrate in a hydrogen fluoride solution.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: January 22, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Xiaoyi Chen, Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Ralph C. Kerns, Ying Rui, Chun Yan, Guowen Ding, Wai-Fan Yau
  • Patent number: 7217665
    Abstract: A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: May 15, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani C. Nallan, Guangxiang Jin, Ajay Kumar
  • Patent number: 7105361
    Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in a high temperature environment to form isolated magnetic regions.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: September 12, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Xiaoyi Chen, Chentsau Ying, Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6984585
    Abstract: A method for removal of residues after plasma etching a film stack comprising a first layer and a sacrificial layer. The method treats a substrate containing the film stack after the first layer of the film stack has been etched to remove residue produced during the etching process. The treatment is performed in a buffered oxide etch wet dip solution that removes the residue and the sacrificial layer.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: January 10, 2006
    Inventors: Chentsau Ying, Xiaoyi Chen, Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6964928
    Abstract: A method for removal of residue after plasma etching a film stack comprising a patterned photoresist material layer, a hard mask layer, a conductive layer, and a magnetic layer, wherein the patterned photoresist material layer and the hard mask layer form a dual mask. The method cleans a substrate containing the film stack after the dual mask of the film stack has been etched to remove residue produced during the etching process. The cleaning step is performed in a solution comprising hydrogen peroxide and ammonium hydroxide that removes the residue.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: November 15, 2005
    Inventors: Chentsau Ying, Xiaoyi Chen, Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6943039
    Abstract: Method of etching a ferroelectric layer includes etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step completely etches through the remaining portion of the ferroelectric layer and also etches lower electrodes. A random access memory apparatus is constructed that includes a first conductive layer, a dielectric layer disposed upon the first conductive layer, a second conductive layer disposed upon the dielectric layer, where such layers form a stack having a sidewall. Further, the sidewall has a protective dielectric film disposed thereon and extending from the second layer down to the dielectric layer.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: September 13, 2005
    Assignee: Applied Materials Inc.
    Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6942813
    Abstract: A method for etching magnetic and ferroelectric materials using a pulsed substrate biasing technique (PSBT) that applies a plurality of processing cycles to the substrate, where each cycle comprises a period of plasma etching without substrate bias and a period of plasma etching with the substrate bias. In exemplary applications, the method is used for fabricating magneto-resistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) devices.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 13, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Xiaoyi Chen
  • Patent number: 6902681
    Abstract: A method of etching high dielectric constant materials (a material with a dielectric constant greater than 4) using a halogen gas, reducing gas, and passivating gas chemistry. An embodiment of the method is accomplished using chlorine, carbon monoxide, and nitrogen to etch and passivate a hafnium dioxide layer.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: June 7, 2005
    Inventors: Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6893893
    Abstract: A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: May 17, 2005
    Inventors: Padmapani C. Nallan, Ajay Kumar, Jeng H. Hwang, Guangxiang Jin, Ralph Kerns
  • Patent number: 6855643
    Abstract: A method for fabricating a gate structure having a polysilicon electrode using an oxygen-free chemistry to etch the polysilicon. In one embodiment, the chemistry further includes nitrogen.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: February 15, 2005
    Inventors: Padmapani C. Nallan, Ajay Kumar
  • Publication number: 20040242005
    Abstract: A method of etching metal layers (e.g., niobium (Nb), titanium (Ti), tantalum (Ta), and the like) using a gas mixture comprising a chlorine-containing gas and a fluorine-containing gas is disclosed. The method provides a high etch selectivity for the metal layers over photoresist.
    Type: Application
    Filed: April 14, 2004
    Publication date: December 2, 2004
    Inventors: Chentsau Ying, Xiaoyi Chen, Padmapani C. Nallan, Ajay Kumar
  • Publication number: 20040209468
    Abstract: A method for fabricating a gate structure of a field effect transistor is disclosed. The gate structure is fabricated by sequentially etching a material stack comprising a gate electrode layer formed on a gate dielectric layer. Prior to etching the gate dielectric layer, polymeric residues formed on the substrate when the gate electrode is etched are removed. The polymeric residue is removed by exposing the substrate to a plasma comprising one or more fluorocarbon containing gases and at least one inert gas. structure.
    Type: Application
    Filed: April 17, 2003
    Publication date: October 21, 2004
    Applicant: Applied Materials Inc.
    Inventors: Ajay Kumar, Padmapani C. Nallan
  • Publication number: 20040206724
    Abstract: A method of plasma etching a metal layer (e.g., titanium (Ti), tantalum (Ta), tungsten (W), and the like) or a metal-containing layer (e.g., tantalum silicon nitride (TaSiN), titanium nitride (TiN), tungsten nitride (WN), and the like) formed on a hafnium-based dielectric material is disclosed. The metal/metal-containing layer is etched using a gas mixture comprising a halogen-containing gas and a fluorine-containing gas. The fluorine within the gas mixture provides a high etch selectivity for the hafnium-based dielectric material.
    Type: Application
    Filed: April 17, 2003
    Publication date: October 21, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Padmapani C. Nallan, Ajay Kumar, Guangxiang Jin
  • Patent number: 6806095
    Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: October 19, 2004
    Inventors: Padmapani C. Nallan, Guangxiang Jin, Ajay Kumar
  • Publication number: 20040173572
    Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 9, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Padmapani C. Nallan, Guangxiang Jin, Ajay Kumar
  • Publication number: 20040173570
    Abstract: A method for etching magnetic and ferroelectric materials using a pulsed substrate biasing technique (PSBT) that applies a plurality of processing cycles to the substrate, where each cycle comprises a period of plasma etching without substrate bias and a period of plasma etching with the substrate bias. In exemplary applications, the method is used for fabricating magneto-resistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) devices.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 9, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Xiaoyi Chen
  • Publication number: 20040171272
    Abstract: A method of fabricating a structure having a tapered profile using a low temperature plasma etch (LTPE) process. In one embodiment, the LTPE process uses a gas comprising carbon tetrafluoride (CF4), trifluoromethane (CHF3), and nitrogen (N2) to fabricate the structure from a material layer of at least one of tantalum (Ta), tantalum nitride (TaN), and the like.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Guangxiang Jin, Padmapani C. Nallan, Chun Yan, Ajay Kumar
  • Publication number: 20040157459
    Abstract: Method of etching a ferroelectric layer comprises etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step completely etches through the remaining portion of the ferroelectric layer and also etches lower electrodes. A random access memory apparatus is constructed that includes a first conductive layer, a dielectric layer disposed upon the first conductive layer, a second conductive layer disposed upon the dielectric layer, where all of said layers form a stack having a sidewall. Further, the sidewall has a protective film disposed thereon and extends from the second layer down to the dielectric layer. The protective sidewall film is fabricated from a dielectric material.
    Type: Application
    Filed: February 11, 2003
    Publication date: August 12, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Chentsau Ying, Padmapani C. Nallan, Ajay Kumar
  • Patent number: 6767824
    Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: July 27, 2004
    Inventors: Padmapani C. Nallan, Ajay Kumar, Guangxiang Jin, Wei Liu
  • Publication number: 20040129361
    Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in a high temperature environment to form isolated magnetic regions.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Xiaoyi Chen, Chentsau Ying, Padmapani C. Nallan, Ajay Kumar