Abstract: Various embodiments are generally directed to an apparatus, system, and other techniques for dynamic and intelligent deployment of a neural network or any inference model on a hardware executor or a combination of hardware executors. Computational costs for one or more operations involved in executing the neural network or inference model may be determined. Based on the computational costs, an optimal distribution of the computational workload involved in running the one or more operations among multiple hardware executors may be determined.

Abstract: Various embodiments are generally directed to an apparatus, system, and other techniques for dynamic and intelligent deployment of a neural network or any inference model on a hardware executor or a combination of hardware executors. Computational costs for one or more operations involved in executing the neural network or inference model may be determined. Based on the computational costs, an optimal distribution of the computational workload involved in running the one or more operations among multiple hardware executors may be determined.

Abstract: In one embodiment, a method provides capturing resource monitoring information for a plurality of applications; accessing the resource monitoring information; and scheduling at least one of the plurality of applications on a selected processing core of a plurality of processing cores based, at least in part, on the resource monitoring information.

Abstract: According to some embodiments, a virtual network driver is provided to support multicored chipsets.

Abstract: A method and apparatus for on-demand CPU licensing. An embodiment of a processor license system includes an agent to determine that a computer processing element in a computer system is faulty or unreliable. The system further includes an activation license manager. The activation license manager provides automatic activation of a spare computer processing element for the computer system upon a determination by the agent that the computer processing element is faulty or unreliable.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a receiver to receive a data packet as a plurality of data vectors over an interconnect. The interconnect includes a plurality of lanes. The apparatus also includes an error detector to detect errors in the data vectors. A buffer is used to store the data vectors received error free. A processor requests a retransmission of the packet if data vectors making up the packet are received with errors. The retransmission of the data packet includes at least a subset of the data vectors being transmitted on different lanes. An assembler reconstructs the data packet once the plurality of data vectors making up the data packet are stored in the buffer. The data packet can be reconstructed even if it was never sent correctly in a single transmission.

Abstract: In one embodiment, the present invention includes a method of analyzing an extensible markup language (XML) file, generating structural information for the XML file, and incorporating the structural information into the XML file. The structural information may correspond to a hierarchy of the file and may further include size information corresponding to elements of the file. In such manner, the structural information may be transmitted with the XML file and used to aid a receiver of the file in parsing. Other embodiments are described and claimed.