Abstract: A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.

Abstract: Updating machine learning models with user data includes executing, by a data processing system, a container including a first machine learning (ML) model, training data for the first ML model, and a library of machine learning functions. The data processing system executes one or more of the machine learning functions of the library. The one or more of the machine learning functions are configured to build a second ML model trained, at least in part, on user training data and to compare accuracy of the first ML model with accuracy of the second ML model. An ML model also may be trained to predict compilation time for circuit designs using training data that includes circuit design features, hardware features of a data processing system, and runtime features from the data processing system.

Abstract: A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.

Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.

Abstract: Strategies are stored in a memory arrangement, and each strategy includes a set of parameter settings for a design tool. The design tool identifies a set of features of an input circuit design and applies classification models to the input circuit design. Each classification model indicates one the strategies, and application of each classification model indicates a likelihood that use of the strategy would improve a metric of the input circuit design based on the set of features of the input circuit design. One strategy of the plurality of strategies is selected based on the likelihood that use of the one strategy would improve the metric of the input circuit design, and the design tool is configured with the set of parameter settings of the one strategy. The design tool then processes the input circuit design into implementation data that is suitable for making an integrated circuit (IC).

Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

Abstract: Methods and apparatus for a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the “sign-off” prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.

Abstract: Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.