Patents by Inventor Padraic C. Shafer
Padraic C. Shafer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080124880Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.Type: ApplicationFiled: September 23, 2006Publication date: May 29, 2008Applicants: Chartered Semiconductor Manufacturing Ltd., International Business Machines CorporationInventors: Wenhe Lin, Randy William Mann, Padraic C. Shafer, Christopher Vincent Baiocco, Zhijoing Luo, Haining S. Yang, Xiangdong Chen
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Patent number: 6869860Abstract: Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.Type: GrantFiled: June 3, 2003Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventors: Michael P. Belyansky, Rama Divakaruni, Laertis Economikos, Rajarao Jammy, Kenneth T. Settlemeyer, Jr., Padraic C. Shafer
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Publication number: 20040248374Abstract: Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.Type: ApplicationFiled: June 3, 2003Publication date: December 9, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Belyansky, Rama Divakaruni, Laertis Economikos, Rajarao Jammy, Kenneth T. Settlemyer, Padraic C. Shafer
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Patent number: 6740539Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: GrantFiled: February 13, 2003Date of Patent: May 25, 2004Assignees: International Business Machines Corporation, Infineon Technologies A.G.Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6664161Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.Type: GrantFiled: May 1, 2002Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic C. Shafer, Joseph F. Shepard, Jr.
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Publication number: 20030207532Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Applicant: International Business Machines CorporationInventors: Michael Patrick Chudzik, Jack Allan Mandelman, Carl John Radens, Rajarao Jammy, Kenneth T. Settlemyer, Padraic C. Shafer, Joseph F. Shepard
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Publication number: 20030153198Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: ApplicationFiled: February 13, 2003Publication date: August 14, 2003Inventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Patent number: 6570256Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: GrantFiled: July 20, 2001Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka
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Publication number: 20030017642Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.Type: ApplicationFiled: July 20, 2001Publication date: January 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard A. Conti, Prakash Chimanlal Dev, David M. Dobuzinsky, Daniel C. Edelstein, Gill Y. Lee, Kia-Seng Low, Padraic C. Shafer, Alexander Simpson, Peter Wrschka