Abstract: In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising: a) depositing on a first underlayer, a blanket of an aluminum compound containing an electrical short reducing amount of an alloy metal in electrical contact with the underlayer; b) depositing a photoresist and exposing and developing to leave patterns of photoresist on the blanket aluminum compound containing an electrical short reducing amount of an alloy metal; and c) reactive ion etching to obtain an aluminum compound containing an alloy metal line characterized by reduced shorts in amounts less than the aluminum compound without said short reducing amount of alloy metal.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

Abstract: Methods and apparatus in accordance with the present invention may employ a layer of tungsten nitride having a ratio of nitrogen to tungsten that is below about 0.7 at and a layer of tungsten formed on the layer of tungsten nitride to obtain a conductive material.

Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising:

Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.