Patents by Inventor Padraig Liam Fitzgerald

Padraig Liam Fitzgerald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240304569
    Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Inventors: Ramji Sitaraman Lakshmanan et al., Bernard Stenson, Padraig Liam Fitzgerald, Oliver Kierse, Michael James Twohig, Michael John Flynn, Laurence Brendan O'Sullivan
  • Patent number: 12027472
    Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: July 2, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Ramji Sitaraman Lakshmanan, Bernard Stenson, Padraig Liam Fitzgerald, Oliver Kierse, Michael James Twohig, Michael John Flynn, Laurence Brendan O'Sullivan
  • Publication number: 20230207489
    Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 29, 2023
    Inventors: Ramji Sitaraman Lakshmanan, Bernard Stenson, Padraig Liam Fitzgerald, Oliver Kierse, Michael James Twohig, Michael John Flynn, Laurence Brendan O'Sullivan
  • Patent number: 11616027
    Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 28, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Ramji Sitaraman Lakshmanan, Bernard Stenson, Padraig Liam Fitzgerald, Oliver Kierse, Michael James Twohig, Michael John Flynn, Laurence Brendan O'Sullivan
  • Publication number: 20210183790
    Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
    Type: Application
    Filed: November 18, 2020
    Publication date: June 17, 2021
    Inventors: Ramji Sitaraman Lakshmanan, Bernard Stenson, Padraig Liam Fitzgerald, Oliver Kierse, Michael James Twohig, Michael John Flynn, Laurence Brendan O'Sullivan
  • Patent number: 10529518
    Abstract: Micro-electromechanical switch (MEMS) devices can be fabricated using integrated circuit fabrication techniques and materials. Such switch devices can provide cycle life and insertion loss performance suiting for use in a broad range of applications including, for example, automated test equipment (ATE), switching for measurement instrumentation (such as a spectrum analyzer, network analyzer, or communication test system), and uses in communication systems, such as for signal processing. MEMS devices can be vulnerable to electrical over-stress, such as associated with electrostatic discharge (ESD) transient events. A solid-state clamp circuit can be incorporated in a MEMS device package to protect one or more MEMS devices from damaging overvoltage conditions. The clamp circuit can include single or multiple blocking junction structures having complementary current-voltage relationships, such as to help linearize a capacitance-to-voltage relationship presented by the clamp circuit.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 7, 2020
    Assignee: Analog Devices Global
    Inventors: Padraig Liam Fitzgerald, Srivatsan Parthasarathy, Javier A. Salcedo
  • Publication number: 20180083439
    Abstract: Micro-electromechanical switch (MEMS) devices can be fabricated using integrated circuit fabrication techniques and materials. Such switch devices can provide cycle life and insertion loss performance suiting for use in a broad range of applications including, for example, automated test equipment (ATE), switching for measurement instrumentation (such as a spectrum analyzer, network analyzer, or communication test system), and uses in communication systems, such as for signal processing. MEMS devices can be vulnerable to electrical over-stress, such as associated with electrostatic discharge (ESD) transient events. A solid-state clamp circuit can be incorporated in a MEMS device package to protect one or more MEMS devices from damaging overvoltage conditions. The clamp circuit can include single or multiple blocking junction structures having complementary current-voltage relationships, such as to help linearize a capacitance-to-voltage relationship presented by the clamp circuit.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Padraig Liam Fitzgerald, Srivatsan Parthasarathy, Javier A. Salcedo
  • Patent number: 8169193
    Abstract: A circuit for dissipating injected parasitic charge includes a circuit stage, a pulse generating circuit and a switch. The circuit stage has an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and has a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: May 1, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Padraig Liam Fitzgerald, Nigel James Hayes
  • Publication number: 20090256531
    Abstract: Disclosed is a method and circuit for dissipating injected parasitic charge including a circuit stage, a pulse generating circuit and a switch. The circuit stage having an input node and an output node that injects a parasitic charge when switched OFF to the output node. The pulse generating circuit can generate a pulsed signal having an input for receiving a control signal. The control signal indicates the circuit stage is switching OFF, and has an output for outputting a pulsed signal in response to the control signal at the input. The pulsed signal can have a predetermined duration. The switch can be configured to be actuated by the pulsed signal output by the pulse generating circuit, and having a terminal connected to the output node of the circuit stage and a terminal connected to circuit to substantially dissipate the injected parasitic charge.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 15, 2009
    Applicant: Analog Devices, Inc.
    Inventors: Padraig Liam FITZGERALD, Nigel James HAYES