Patents by Inventor Pai-Chieh Wang
Pai-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10720361Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: GrantFiled: July 15, 2019Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
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Publication number: 20190341310Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
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Patent number: 10354920Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: GrantFiled: August 8, 2016Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
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Patent number: 10163724Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.Type: GrantFiled: March 1, 2012Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pai-Chieh Wang, Yimin Huang
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Patent number: 9941372Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: GrantFiled: May 9, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Publication number: 20160351451Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: ApplicationFiled: August 8, 2016Publication date: December 1, 2016Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
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Publication number: 20160254360Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Patent number: 9412883Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: GrantFiled: November 22, 2011Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen
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Patent number: 9337293Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.Type: GrantFiled: February 22, 2013Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tsung Yao Wen, Jyh-Huei Chen
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Patent number: 9269833Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.Type: GrantFiled: November 22, 2011Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang
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Publication number: 20130228878Abstract: A semiconductor device and method for fabricating a semiconductor device are disclosed.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pai-Chieh WANG, Yimin HUANG
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Publication number: 20130230952Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pai-Chieh WANG, Yimin HUANG
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Publication number: 20130126955Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang
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Publication number: 20130126953Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pai-Chieh Wang, Tung-Heng Hsieh, Yimin Huang, Chung-Hui Chen