Abstract: A binary arithmetic coding apparatus is implemented in a video encoder chip. The binary arithmetic coding apparatus outputs a code word according to a syntax element value, and includes a look-up table (LUT), a suffix generator and a combiner. The LUT outputs a first binary string according to the syntax element value. The suffix generator performs exp-Golomb binarization on the syntax element value to generate a second binary string. When the syntax element value is smaller than or equal to a threshold, the first binary string is outputted as the code word. When the syntax element value is greater than the threshold, the combiner combines the first binary string and the second binary string to form the code word.

Abstract: A video compression circuit including a video pre-processor, a macroblock data storage unit and a video processor is provided. When fulfilled by an input video signal, the video pre-processor converts the input video signal to generate a macroblock data. The macroblock data storage unit alternatively and temporally stores the macroblock data generated from the video pre-processor. The video processor alternatively reads the macroblock data stored in the macroblock data storage unit, and compresses the readout macroblock data to an output video signal.

Abstract: A video compression circuit including a video pre-processor, a macroblock data storage unit and a video processor is provided. When fulfilled by an input video signal, the video pre-processor converts the input video signal to generate a macroblock data. The macroblock data storage unit alternatively and temporally stores the macroblock data generated from the video pre-processor. The video processor alternatively reads the macroblock data stored in the macroblock data storage unit, and compresses the readout macroblock data to an output video signal.