Abstract: A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.

Abstract: A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: A silicon etching method includes providing a substrate assembly including an exposed silicon region and an exposed oxide region. An etch composition including an ammonium fluoride component, an inorganic acid component, and an oxidizing agent is also provided. The etch composition has a pH in the range of about 7.0 to about 8.0. The substrate assembly is exposed to the etch composition. Exposing the substrate assembly to the etch composition may result in etching the exposed silicon region at an etching rate that is greater than about 3 times the etching rate of the exposed oxide region and/or etching the silicon region at an etch rate greater than about 9 Å/minute. The etching method may be used in forming isolation structures. Further, etch compositions for performing the desired etch are provided.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.