Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

Abstract: In a method of manufacturing an electronic package, first grooves are formed on a circuit structure and a second groove is formed in each of the first grooves to allow the circuit structure to become circuit layers. Owing to the second groove is narrower than the first groove, each of the circuit layers has an encircled surface and a notch located on the encircled surface. When a shielding layer is provided to cover an encapsulating body located on the circuit layer, a space of the notch is not covered by the shielding layer such that a portion to be removed of the shielding layer will not remain on the electronic package to become burr after removing the portion to be removed.

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.

Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.

Abstract: A method of manufacturing an electronic package module is provided. The method forms dual-side and selective encapsulation by using a dam filling process and a sacrificial layer. Electronic components are protected from electromagnetic interference while not interfering functioning of specific electronic components which are not encapsulated.

Abstract: A manufacturing method of selective electronic packaging device includes the following. A plurality of electronic components is disposed on a surface of a substrate. A photo-sensitive resin material is formed on the surface of the substrate. UV-light is irradiated to the photo-sensitive resin material to form an embankment structure. An encapsulating material is filled a protective area surrounded by the embankment structure. The encapsulating material covers at least one electronic component. The encapsulating material is solidified to form an encapsulating member, and the encapsulating member covers at least one electronic component.

Abstract: The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.

Abstract: The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract: A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.

Abstract: A method of manufacturing a chip on film (COF) is provided, including: providing a flexible circuit board; and forming a plurality of leads on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um and a cross-section shape is substantially rectangular. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board, is provided. Each lead has a thickness of 8 um˜15 um, and lead widths of the leads are based on pitch widths of a plurality of bumps corresponding to the leads. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um, and a lead width of each of the leads is greater than a bump width minus 4 um.

Abstract: A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.

Abstract: A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.

Abstract: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of first protruding portions. The polygonal body has a first planar surface and a corresponding second planar surface. The second planar surface of the polygonal body is in contact with the chip. The first protruding portions are disposed on the first planar surface at the corner regions of the polygonal body. By modifying the geometric shape of the bonding pad, the yield of bonding the chip structure and another device together through the bonding pad is increased.

Abstract: A semiconductor package includes a chip and a carrier. The chip has an active surface and a lateral surface. The active surface has a number of first bumps and a number of second bumps. The first bumps are spaced by the second bumps. The first bumps are farther from the lateral surface than the second bumps are. The carrier has a base and a number of first inner leads. Each first inner lead has a body portion and a distal end bonding portion. The width of the body portion is smaller than that of the distal end bonding portion. The distal end bonding portions are electrically bonded to the first bumps such that the chip is disposed on the carrier, and each of the body portions is located between the two adjacent second bumps.

Abstract: A chip structure and a bonding pad are provided. The chip structure comprises a chip and at least a bonding pad. The chip has an active surface. The bonding pad is disposed on the active surface of the chip. The bonding pad comprises a polygonal body and a plurality of first protruding portions. The polygonal body has a first planar surface and a corresponding second planar surface. The second planar surface of the polygonal body is in contact with the chip. The first protruding portions are disposed on the first planar surface at the corner regions of the polygonal body. By modifying the geometric shape of the bonding pad, the yield of bonding the chip structure and another device together through the bonding pad is increased.

Abstract: An electrical connection structure for electrically connecting with a chip and a bearing element is provided. The chip has a first surface. The bearing element has a second surface corresponding to the first surface. The electrical connection structure includes two outer contact points on the first surface, M inner contact points on the first surface and correspond to the inner side of the first surface, two outer conducting wires on the second surface, and M inner conducting wires on the second surface and corresponding to the M inner contact points. The chip and the bearing element are electrically connected via the electrical contact between the two outer contact points and the two outer conducting wires, and the electrical connection between the M inner contact points and the M inner conducting wires. M is a positive integer greater than or equal to 2.

Abstract: A semiconductor package includes a chip and a carrier. The chip has an active surface and a lateral surface. The active surface has a number of first bumps and a number of second bumps. The first bumps are spaced by the second bumps. The first bumps are farther from the lateral surface than the second bumps are. The carrier has a base and a number of first inner leads. Each first inner lead has a body portion and a distal end bonding portion. The width of the body portion is smaller than that of the distal end bonding portion. The distal end bonding portions are electrically bonded to the first bumps such that the chip is disposed on the carrier, and each of the body portions is located between the two adjacent second bumps.