Patents by Inventor PaiLu Dennis WANG

PaiLu Dennis WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory inspecting method and memory inspecting system
    Patent number: 11195592
    Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 7, 2021
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: PaiLu Dennis Wang, Lien-Sheng Yang
  • MEMORY INSPECTING METHOD AND MEMORY INSPECTING SYSTEM
    Publication number: 20210257042
    Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.
    Type: Application
    Filed: September 2, 2020
    Publication date: August 19, 2021
    Inventors: PaiLu Dennis WANG, Lien-Sheng YANG