Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A ferroelectric dielectric for microwave applications is provided comprising a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapor, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material comprising lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

Abstract: A ferroelectric dielectric for microwave applications is provided comprising a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapour, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material comprising lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

Abstract: A ferroelectric dielectric for microwave applications is provided including a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapour, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material including lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

Abstract: A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Abstract: An improved electrode structure compatible with ferroelectric capacitor dielectrics is provided. In particular, a multilayer electrode having improved adhesion to ferroelectric materials such as PZT is formed comprising a first layer of a noble metal, a second layer of another metal and a thicker layer of the noble metal, which are annealed to cause controlled interdiffusion of the layers forming a mixed metal surface layer having a rough interface with the dielectric layer. For example, the first two layers comprise relatively thin .about.200 .ANG. layers of Pt and Ti, and then a thicker layer of the main, first, electrode material is deposited on top. Non-uniform interdiffusion of the layers during annealing causes intermixing of the Pt and Ti layers at the interfaces forming a Pt/Ti alloy having a rough surface. The rough surface, and particularly hillocks formed at the interface, penetrate into the ferroelectric films, and anchor the electrode material to the dielectric.

Abstract: An integrated circuit structure including dielectric barrier layer compatible with perovskite ferroelectric materials and comprising zirconium titanium oxide, ZrTiO.sub.4, and a method of formation of the dielectric barrier layer by sol gel process is described. The amorphous, mixed oxide barrier layer has excellent dielectric properties up to GHz frequencies, and crystallizes above 800.degree. C., facilitating device processing. In particular, the barrier layer is compatible with lead containing perovskites, including PZT and PLZT ferroelectric dielectrics for example for application in non-volatile memory cells, and high value capacitors for integrated circuits, using silicon or GaAs integrated circuit technologies.

Abstract: An improved electrode structure compatible with ferroelectric capacitor dielectrics is provided. In particular, a multilayer electrode having improved adhesion to ferroelectric materials such as PZT is formed comprising a first layer of a noble metal, a second layer of another metal and a thicker layer of the noble metal, which are annealed to cause controlled interdiffusion of the layers forming a mixed metal surface layer having a rough interface with the dielectric layer. For example, the first two layers comprise relatively thin .about.200.ANG. layers of Pt and Ti, and then a thicker layer of the main, first, electrode material is deposited on top. Non- uniform interdiffusion of the layers during annealing causes intermixing of the Pt and Ti layers at the interfaces forming a Pt/Ti alloy having a rough surface. The rough surface, and particularly hillocks formed at the interface, penetrate into the ferroelectric films, and anchor the electrode material to the dielectric.

Abstract: A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Abstract: A method of detecting opaque defects on a reticle used to define die patterns during semiconductor device fabrication in which a comparison is made of reflected light levels between an image die containing the developed photo-sensitive resist of a top layer with a reference die which contains only previously formed layers. The comparison is limited to areas of the device where there is no image pattern formed by the resist. A defect is detected whenever there is a difference in the recorded levels detected during the comparison.