Abstract: An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

Abstract: An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

Abstract: A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.