Patents by Inventor Pak Shing Chau
Pak Shing Chau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230409072Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: June 7, 2023Publication date: December 21, 2023Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 11709525Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: June 1, 2022Date of Patent: July 25, 2023Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Publication number: 20220365552Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: June 1, 2022Publication date: November 17, 2022Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 11378998Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: November 23, 2020Date of Patent: July 5, 2022Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Publication number: 20210173427Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: November 23, 2020Publication date: June 10, 2021Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 10877511Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: September 10, 2019Date of Patent: December 29, 2020Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 10855413Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: GrantFiled: April 29, 2016Date of Patent: December 1, 2020Assignee: Rambus Inc.Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Publication number: 20200089270Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: September 10, 2019Publication date: March 19, 2020Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 10496126Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: December 27, 2016Date of Patent: December 3, 2019Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Publication number: 20170177021Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: December 27, 2016Publication date: June 22, 2017Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 9568942Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: December 7, 2015Date of Patent: February 14, 2017Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 9564885Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.Type: GrantFiled: November 16, 2012Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Pak Shing Chau, Wayne S. Richardson, Jun Kim
-
Publication number: 20160352474Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: ApplicationFiled: April 29, 2016Publication date: December 1, 2016Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Publication number: 20160161977Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: ApplicationFiled: December 7, 2015Publication date: June 9, 2016Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Patent number: 9356743Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: GrantFiled: June 27, 2014Date of Patent: May 31, 2016Assignee: Rambus Inc.Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Patent number: 9235537Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.Type: GrantFiled: October 19, 2012Date of Patent: January 12, 2016Assignee: Rambus Inc.Inventors: Jun Kim, Pak Shing Chau, Wayne S. Richardson
-
Publication number: 20150078426Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: ApplicationFiled: June 27, 2014Publication date: March 19, 2015Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Publication number: 20140333361Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.Type: ApplicationFiled: November 16, 2012Publication date: November 13, 2014Applicant: Rambus Inc.Inventors: Pak Shing Chau, Wayne S. Richardson, Jun Kim
-
Patent number: 8812918Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: GrantFiled: November 7, 2011Date of Patent: August 19, 2014Assignee: Rambus Inc.Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
-
Patent number: 8812919Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.Type: GrantFiled: June 12, 2013Date of Patent: August 19, 2014Assignee: Rambus Inc.Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher