Abstract: A semiconductor component includes a semiconductor substrate (310) having a first conductivity type, a first semiconductor device (320) at least in a first portion of the semiconductor substrate, and a second semiconductor device (330, 310) at least in a second portion of the semiconductor substrate. The first semiconductor device includes a first electrode region (321), a second electrode region (322), a body region (323), and an isolation region (324) in the first portion of the semiconductor substrate. The body region has the first conductivity type, and the first electrode region, the second electrode region, and the isolation region have a second conductivity type. The second electrode region has a different doping concentration than the first electrode region, and the body region is isolated from the second portion of the semiconductor substrate by the isolation region and the first electrode region.

Abstract: A semiconductor component includes a semiconductor substrate (310) having a first conductivity type, a first semiconductor device (320) at least in a first portion of the semiconductor substrate, and a second semiconductor device (330, 310) at least in a second portion of the semiconductor substrate. The first semiconductor device includes a first electrode region (321), a second electrode region (322), a body region (323), and an isolation region (324) in the first portion of the semiconductor substrate. The body region has the first conductivity type, and the first electrode region, the second electrode region, and the isolation region have a second conductivity type. The second electrode region has a different doping concentration than the first electrode region, and the body region is isolated from the second portion of the semiconductor substrate by the isolation region and the first electrode region.

Abstract: A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.

Abstract: A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.

Abstract: A method of fabricating a fast-switching, low-R(on) insulated-gate bipolar transistor including providing an N-type semiconductor wafer with a planar surface, forming a thin heavily-doped layer, having a concentration in the range of 3.times.10.sup.17 /cm.sup.3 to 1.times.10.sup.19 /cm.sup.3, in the wafer adjacent the planar surface, providing a P-type semiconductor wafer, and bonding a surface of the P-type wafer to the planar surface of the N-type wafer. An emitter and a gate are then formed in the N-type wafer in the usual manner and a collector is formed on the P-type wafer.