Abstract: The present invention discloses a System comprising a number of plug-in units, where each of the plug-in units that is hosting a device processor is comprising two flash memory banks, and further a traffic and a control system that are separated within said node and/or each of said plug-in units have separate traffic and control system. The present invention further discloses a method for non interruptible installation, operation, maintenance, supervising and hardware or software upgrading the telecom or data communication node.

Abstract: The present invention is related to buffering between synchronous circuits communication via a global synchronous bus, and in particular an arrangement for reducing the busload in a TDM bus system by, in a preferred embodiment, introducing a local TEM data bus and an active buffer including a CPU controlled logic between the transceiver loads and the TDM bus. The active buffers in the TX and RX direction together provides a time delay for data travelling from a first local TDM bus out on the backplane TDM bus and back to a second local TDM of the exact duration of one TDM frame or an integer number of TDM frames.

Abstract: An arrangement for transmitting independent serial data streams through synchronous Time Division Multiplexing (TDM) switches with a number of input and output lines is disclosed. At the receiving side of a switch, there is one data buffer per TDM bus buffering the data before transfer on the bus. A connection table associated with each buffer includes entries addressing the bytes in the buffer. The order of the addresses determines the order of the bytes as they are transferred over the bus. Also, at the transmitting side, there is one data buffer per bus, but only one common connection table. The connection table is divided into one memory area per output line, and determines the order of the data bytes, as they will occur at the respective output lines.

Abstract: A method and an arrangment for reducing phase jumps in a frame synchronisation signal when switching between synchronisation signal when switching between synchronisation reference sources are disclosed. A new reference signal to which each of the two reference sources (signals) are phase locked, and has frequency n times the respective reference signal, is generated. A selection signal selects the new reference signal to be used, and the selected one is then divided back to its original frequency creating an input signal to a phase-locked loop generating the resulting frame synchronisation signal. In this way, the maximum phase jumps are reduced from one period of the original reference signals to one period of the new reference signal. The invention is particularly applicable for reducing phase jumps on a master frame synchronisation signal in a PDH system.

Abstract: The present invention discloses an arrangement providing a better utilization of the bus buffer memory in a data node, e.g. a switch. By using one scheduler on both sides of the switch and one timer for each output and input lines in an inventive way for transferring data to and from the time slot buses in the switch, the memory recourses therein are utilized in a more optimal way, also the present invention. Also, by setting up the scheduler parameters in a special way it is possible to obtain very short delays through the TDM switch. The present invention allows for both structured modus (bytes in transfer on the time slot buses are made identifiable) with constant delay and dependent timing, and for unstructured modus with minimum delay and both independent and dependent timing. This contributes to make the invention very useful and unique.

Abstract: The present invention discloses a method and an arrangement providing transmission of data through a node, e.g. a switch, having different input and output line interfaces in a wide range of data speed, without introducing any loss of bits, but still maintaining the nominal bit rate. This is achieved by means of a very simple and flexible implementation. At the receiving side of the switch, one extra bit per frame is transferred over the time slot bus of the switch if the number of bits in the corresponding FIFO of the input line exceeds a predefined upper limit. In contrast, one bit less per frame is transferred if the number of bits in the corresponding FIFO of the input line goes below a predefined lower limit. At the transmitting side of the switch, a FLL circuit regulates the data rate out of the FIFOs. The FLL circuit is implemented as a P-regulator having i.a. the fill degree of the FIFO as a direct input.