Abstract: A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Abstract: A varistor array can include a monolithic body including a plurality of dielectric layers. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal on a first end of the monolithic body, a first plurality of electrodes connected with the first external terminal, a second external terminal on a second end of the monolithic body, and a second plurality of electrodes connected with the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes at an overlapping area that is insensitive to a relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is less than a threshold. A second varistor can be formed in the monolithic body that is distinct from the first varistor.

Abstract: A varistor can include a monolithic body including a plurality of dielectric layers stacked in a Z-direction that is perpendicular to a longitudinal direction. The monolithic body can have a first end and a second end that is spaced apart from the first end in the longitudinal direction. A first external terminal can be disposed along the first end. A second external terminal can be disposed along the second end. A first plurality of electrodes can be connected with the first external terminal and can extend from the first end towards the second end of the monolithic body. A second plurality of electrodes can be connected with the second external terminal and can extend from the second end towards the first end of the monolithic body. At least one of the first external terminal or the second external terminal can include a conductive polymeric composition.

Abstract: A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Abstract: In general, a varistor including a passivation layer and a method of forming such a varistor are disclosed. The varistor comprises a ceramic body comprising a plurality of alternating dielectric layers and electrode layers. The varistor also comprises a first external terminal on a first end surface and a second external terminal on a second end surface opposite the first end surface wherein at least two side surfaces extend between the first end surface and the second end surface. The varistor also comprises a passivation layer on at least one side surface of the ceramic body between the first external terminal and the second external terminal. The passivation layer includes a phosphate and a metal additive including an alkali metal, an alkaline earth metal, or a mixture thereof. The passivation layer has an average thickness of from 0.1 microns to 30 microns.

Abstract: The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

Abstract: A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Abstract: The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

Abstract: A method is disclosed for making a multilayer electronic device. The method includes placing a screen printing mask on a layer of support material and printing a conductive pattern on a layer of support material using the screen printing mask. The conductive pattern includes a plurality of electrode shapes including respective central enlarged portions. The method includes cutting the layer of support material and conductive pattern along a plurality of cutting lines intersecting the central enlarged portions such that at least one of the plurality of electrode shapes is divided into a pair of electrodes along a cutting width. The cutting width is indicative of a cutting accuracy associated with at least one of the cutting lines.

Abstract: The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

Abstract: In general, a varistor including a passivation layer and a method of forming such a varistor are disclosed. The varistor comprises a ceramic body comprising a plurality of alternating dielectric layers and electrode layers. The varistor also comprises a first external terminal on a first end surface and a second external terminal on a second end surface opposite the first end surface wherein at least two side surfaces extend between the first end surface and the second end surface. The varistor also comprises a passivation layer on at least one side surface of the ceramic body between the first external terminal and the second external terminal. The passivation layer includes a phosphate and a metal additive including an alkali metal, an alkaline earth metal, or a mixture thereof. The passivation layer has an average thickness of from 0.1 microns to 30 microns.

Abstract: A low aspect ratio varistor is disclosed. The varistor may have a rectangular configuration defining first and second opposing side surfaces offset in a widthwise direction and first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first electrode layer including a first electrode having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include a second electrode layer including a second electrode having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include first and second terminals adjacent and connected with the first and second opposing end surfaces, respectively. At least one of the first or second electrodes may have an electrode aspect ratio less than about 1.

Abstract: The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

Abstract: A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

Abstract: A low aspect ratio varistor is disclosed. The varistor may have a rectangular configuration defining first and second opposing side surfaces offset in a widthwise direction and first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first electrode layer including a first electrode having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include a second electrode layer including a second electrode having an electrode length in the lengthwise direction and an electrode width in the widthwise direction. The varistor may also include first and second terminals adjacent and connected with the first and second opposing end surfaces, respectively. At least one of the first or second electrodes may have an electrode aspect ratio less than about 1.

Abstract: A method is disclosed for making a multilayer electronic device. The method includes placing a screen printing mask on a layer of support material and printing a conductive pattern on a layer of support material using the screen printing mask. The conductive pattern includes a plurality of electrode shapes including respective central enlarged portions. The method includes cutting the layer of support material and conductive pattern along a plurality of cutting lines intersecting the central enlarged portions such that at least one of the plurality of electrode shapes is divided into a pair of electrodes along a cutting width. The cutting width is indicative of a cutting accuracy associated with at least one of the cutting lines.

Abstract: The present invention relates generally to methods for the synthesis of various solids such as diamonds, diamonds films, boron nitride and other similar materials. This invention specifically relates to utilizing novel sources of reaction species (e.g., in the case of diamond formation, novel sources of carbon and/or hydrogen and/or seeds) for the manufacture of various materials and the use of such materials for various commercial purposes.

Abstract: Method of providing a semiconductor device with an inorganic electrically insulative layer, the device having exposed semiconductor surfaces and electrically conductive metal end terminations, in which the device is reacted with phosphoric acid to form a phosphate on the exposed surfaces of the semiconductor but not on the metal end terminations, and in which the device is thereafter barrel plated in a conventional electrical barrel plating process and the plating is provided only on the end terminations because the phosphate is not electrically conductive.

Abstract: A method of providing a semiconductor device with an inorganic electrically insulative layer, the device having exposed semiconductor surfaces and electrically conductive metal end terminations, in which the device is reacted with phosphoric acid to form a phosphate on the exposed surfaces of the semiconductor but not on the metal end terminations, and in which the device is thereafter barrel plated in a conventional electrical barrel plating process and the plating is provided only on the end terminations because the phosphate is not electrically conductive.