Patents by Inventor Paliath Narendran

Paliath Narendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital circuit design verification
    Patent number: 4872126
    Abstract: A system and method for modeling digital circuit elements to enable verification of circuit design by formal proofs using a computerized theorem proving system, is disclosed.
    Type: Grant
    Filed: January 11, 1988
    Date of Patent: October 3, 1989
    Assignee: General Electric Company
    Inventors: William J. Premerlani, David R. Musser, Paliath Narendran