Abstract: The present disclosure provides for encoding the signal using a window-based partitioned sequence of literals and then operating over this sequence to determine relevant periodic artifacts. A signal can be received, and then the signal can be abstracted to a sequence of literals. Repeating sub-sequences of literals can be identified in windows of time that increase in width until a repeating sub-sequence is found. Once a repeating sub-sequence is found, the window of time is shifted, and the process repeated. Once the temporal variations of the artifacts are known for the signal, the reference voltage at each of the time periods can be found by resampling the signal in different windows of time, finding temporary reference voltages that are means of samples in each window, determining the reference voltages for each time period, and then determining the DC reference based on a median of the list of reference values.

Abstract: Various embodiments disclosed herein provide for a glitch detection and level detection method that use information contained in the signal itself to determine at which resolution or granularity the glitch detection and level detection operates. In particular, the glitch detection method comprises defining a glitch in terms of a change in the area under the waveform which can serve to disambiguate glitches from noises and other transient side effects of level transmissions. Likewise, the level detection method uses an entropy-based metric to identify levels that are significant in context of the entire signal and not in absolute terms.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Abstract: A system and method for providing control timing for a vehicle system at the design level. The method includes defining component timing specifications in a parametric form at a system level and at a sub-system level; mathematically representing the timing specifications in a system model; providing a constraint extraction algorithm that extracts timing constraints from the mathematical representations; using the constraint extraction algorithm to generate a plurality of linear equations that define the constraints; solving for real time constraint ranges from parameters in the linear equations; and selecting values from the real time constraint ranges to be used in the mathematical representations. In non-limiting embodiments, the constraint extraction algorithm can be a boundary discovery algorithm or a proof-tree.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Abstract: A system and method for providing control timing for a vehicle system at the design level. The method includes defining component timing specifications in a parametric form at a system level and at a sub-system level; mathematically representing the timing specifications in a system model; providing a constraint extraction algorithm that extracts timing constraints from the mathematical representations; using the constraint extraction algorithm to generate a plurality of linear equations that define the constraints; solving for real time constraint ranges from parameters in the linear equations; and selecting values from the real time constraint ranges to be used in the mathematical representations. In non-limiting embodiments, the constraint extraction algorithm can be a boundary discovery algorithm or a proof-tree.