Abstract: A system and method is disclosed for integrating a trading partner into an XML based Internet. The system is operable to access the Internet to register a business name with one or more XML naming systems and register a business name with one or more XML naming systems. The system is further operable to receive an XML based address from the one or more XML naming systems. The system is still further operable to assign the XML based address to an authoritative XML naming system and map the XML based address to the Internet.

Abstract: A system and method is disclosed for integrating a trading partner into an XML based Internet. The system is operable to access the Internet to register a business name with one or more XML naming systems and register a business name with one or more XML naming systems. The system is further operable to receive an XML based address from the one or more XML naming systems. The system is still further operable to assign the XML based address to an authoritative XML naming system and map the XML based address to the Internet.

Abstract: In one embodiment, a system is provided for managing a centrally managed master repository for core enterprise reference data associated with an enterprise. A centralized master repository contains the reference data, the reference data being associated with multiple schemas, each schema including one or more data models for reference data, each data model including one or more fields. A data management services framework coupled to the repository provides services for managing the reference data in the repository. The services framework supports a master schema including a union of multiple models and associated fields in the multiple schemas. The services framework also supports a thesaurus including, for each field in the master schema, a set of synonyms each representing a mapping between the field in the master schema and a corresponding field in a particular one of the multiple schemas.

Abstract: A computer-implemented marketplace (16) for providing financial transaction services to participants (12, 14, 60, 62) in connection with commercial transactions involving the participants (12, 14, 60, 62) includes a database (22). The database (22) contains registration information for types of transactions available to participants (12, 14, 60, 62) and participation criteria for each participant (12, 14, 60, 62) that specifies types of transactions in which the participant (12, 14, 60, 62) is willing to participate. Processes (24) provide associated financial transaction services for the participants (12, 14, 60, 62) in connection with ongoing transactions involving the participants (12, 14, 60, 62).

Abstract: In one embodiment, a system is provided for managing a centrally managed master repository for core enterprise reference data associated with an enterprise. A centralized master repository contains the reference data, the reference data being associated with multiple schemas, each schema including one or more data models for reference data, each data model including one or more fields. A data management services framework coupled to the repository provides services for managing the reference data in the repository. The services framework supports a master schema including a union of multiple models and associated fields in the multiple schemas. The services framework also supports a thesaurus including, for each field in the master schema, a set of synonyms each representing a mapping between the field in the master schema and a corresponding field in a particular one of the multiple schemas.

Abstract: A system and method is disclosed for integrating a trading partner into an XML based Internet. The system is operable to access the Internet to register a business name with one or more XML naming systems and register a business name with one or more XML naming systems. The system is further operable to receive an XML based address from the one or more XML naming systems. The system is still further operable to assign the XML based address to an authoritative XML naming system and map the XML based address to the Internet.

Abstract: In one embodiment, a system is provided for managing a centrally managed master repository for core enterprise reference data associated with an enterprise. A centralized master repository contains the reference data, the reference data being associated with multiple schemas, each schema including one or more data models for reference data, each data model including one or more fields. A data management services framework coupled to the repository provides services for managing the reference data in the repository. The services framework supports a master schema including a union of multiple models and associated fields in the multiple schemas. The services framework also supports a thesaurus including, for each field in the master schema, a set of synonyms each representing a mapping between the field in the master schema and a corresponding field in a particular one of the multiple schemas.

Abstract: A system for service transaction brokering among distributed marketplaces includes a first marketplace (102) that provides at least a first service and a second marketplace (102) that provides at least a second service. The system also includes a service transaction broker (104) that is coupled to the first and second marketplaces (102) and that provides at least the second service of the second marketplace (102) to a user (200) that is coupled to the first marketplace (102) in response to the user (200) communicating a service request.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

Abstract: A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anistropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

Abstract: DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.

Abstract: A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignement marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.

Abstract: A static random access memory, wherein power consumption is reduced by using asynchronous edge-triggered power down gates to power up only elements in the critical circuit path for only as long as necessary to access the memory. Thus, power consumption in the memory is reduced to nearly an absolute minimum. This invention uses the address transition clock to provide an asynchronous power up function to various parts of the static RAM so that only the circuit which is propagating the signal is powered up and the power is held high just long enough for the signal to propagate. This is performed using intrinsic timing elements of the RAM critical path so that the timing of the signal and power cycles track each other.

Abstract: A process for forming backside contacts includes first forming an etch stop layer (12) beneath the surface of a silicon substrate. An active circuit is then formed in the silicon surface and associated metal interconnecting layers formed on the upper surface of the substrate. A planarizing layer is then formed on the upper surface of the substrate which is operable to be connected to a mechanical support. Thereafter, the backside of the substrate is etched away up to the etch stop layer (12). The thickness of the remaining substrate between the metal layers on the upper surface and the etch stop layer is sufficiently thin that the alignment marks on the upper surface can be seen through the substrate. These alignment marks are utilized to form vias from the backside to the active elements and then deposit and pattern interconnecting layers on the backside.

Abstract: An orthogonal chip mount system module (10) comprising a base module (12), an interconnect chip (14), orthogonal slots (16) and semiconductor chips (18) is provided. The interconnect chip (14) is fixed to the base module (12) by high thermal conductivity epoxy. The semiconductor chips (18) are interference fitted into the slots (16). Solder pads (20) on the semiconductor chips (18) are aligned with solder pads (22) on the interconnect chip (14) and the system module (10) is then heated to the reflow temperature of the solder forming joints (24).

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention). A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: A micropackage for providing high density, three dimensional packaging of integrated circuit chips. A chipmount (10) includes a plurality of channels (36) on the bottom surface thereof for holding a corresponding plurality of integrated circuit chips (16). A shallow cavity (34) is formed on the top surface of the chipmount (10) for holding another integrated circuit (14). Metallization interconnections (22) are formed on the top and bottom surfaces of the chipmount (10) and are terminated by solder pads (24, 39). Conductive conduits (26) are formed through the chipmount (10) for providing electrical continuity between an integrated circuit chip (14) mounted on the top side, to other integrated circuit chips (16) mounted on the bottom side of the chipmount. Other conductive conduits (30, 32) and a bridging member (28) insulates intersecting conductive paths (48, 50). The micropackage is fabricated with standard silicon technology.