Abstract: Under software control, a loss of clock detect circuit (24) can be enabled to detect loss of clock. A plurality of different clock signals, including the input reference clock (34) to the PLL (12) and the feedback (36) from the PLL (12), are monitored by the loss of clock circuit (24). When the currently selected system clock (38) signal is lost, a control circuit (28) can select an optimal back-up clocking mode based on which clock signals were lost. One such selectable mode is to utilize the input reference clock (34) directly instead of the PLL (12). Another such selectable mode is to utilize the PLL (12) in a self-clocked mode to provide the system clock (38).