Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Abstract: The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Abstract: A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.

Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

Abstract: A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

Abstract: A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.

Abstract: The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Abstract: A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

Abstract: An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

Abstract: A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.

Abstract: A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.

Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

Abstract: A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.

Abstract: A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: A method and apparatus for designing very large scale integrated circuit devices, most particularly level sensitive scan design (LSSD) devices, by inclusion of a plurality of distributed delay lines originating at input terminals of the device, and controlling the inhibiting and enabling of driver circuits connected to the output terminals of the device, as required to regulate operation of device drivers during a plurality of testing operations.