Patents by Inventor Pamela S. Hempstead

Pamela S. Hempstead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8806112
    Abstract: A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Vinay Ashok Somanache, Michael S. Hicken, Pamela S. Hempstead, Timothy W. Swatosh, Jackson L. Ellis, Martin S. Dell
  • Patent number: 8645618
    Abstract: A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 4, 2014
    Assignee: LSI Corporation
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Michael S. Hicken, Timothy W. Swatosh, Martin S. Dell, Pamela S. Hempstead
  • Publication number: 20130019053
    Abstract: A flash media controller including one or more dedicated data transfer paths, one or more flash lane controllers, and one or more flash bus controllers. The one or more flash lane controllers are generally coupled to the one or more dedicated data transfer paths. The one or more flash bus controllers are generally coupled to the one or more flash lane controllers.
    Type: Application
    Filed: March 28, 2012
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Timothy W. Swatosh, Pamela S. Hempstead, Jackson L. Ellis, Michael S. Hicken, Martin S. Dell
  • Publication number: 20130019050
    Abstract: A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.
    Type: Application
    Filed: December 21, 2011
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Michael S. Hicken, Timothy W. Swatosh, Martin S. Dell, Pamela S. Hempstead
  • Publication number: 20130019051
    Abstract: A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.
    Type: Application
    Filed: December 22, 2011
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Michael S. Hicken, Pamela S. Hempstead, Timothy W. Swatosh, Jackson L. Ellis, Martin S. Dell
  • Publication number: 20130019052
    Abstract: An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to maintain die-based information used for operation of a flash lane controller (FLC). The second circuit may be configured to manage contexts that are actively being processed by the flash lane controller (FLC). The third circuit may be configured to perform pipeline execution of a plurality of the contexts managed by the second circuit.
    Type: Application
    Filed: January 5, 2012
    Publication date: January 17, 2013
    Inventors: Vinay Ashok Somanache, Jackson L. Ellis, Pamela S. Hempstead, Timothy W. Swatosh, Michael S. Hicken, Martin S. Dell