Patents by Inventor Pamela S. Trammel

Pamela S. Trammel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6709882
    Abstract: A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: March 23, 2004
    Assignee: Lightwave Microsystems Corporation
    Inventors: Pamela S. Trammel, Jonathan G. Bornstein, David H. Menche
  • Patent number: 6704487
    Abstract: A method of making an optical waveguide structure for an active PLC device having a reduced dn/dt birefringence. The method includes the step of forming a waveguide core layer on a bottom cladding, the waveguide core layer having a higher refractive index than the bottom cladding. The waveguide core layer is then etched to define a waveguide core. A top cladding is subsequently formed over the waveguide core and the bottom cladding. The top cladding also has a lower refractive index than the waveguide core. The top cladding is then etched to define a first trench and a second trench parallel to the waveguide core. The first trench and the second trench are configured to relieve a stress on the waveguide core. This stress can be induced by a heater, as in a case where the active PLC is a thermo-optic PLC. The first trench and the second trench can extend from an upper surface of the top cladding to an upper surface of the bottom cladding.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: March 9, 2004
    Assignee: Lightwave Microsystems Corporation
    Inventors: Farnaz Parhami, Alice Liu, Pamela S. Trammel
  • Patent number: 6579777
    Abstract: A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: June 17, 2003
    Assignees: Cypress Semiconductor Corp., LSI Logic Corporation
    Inventors: Ting P. Yen, Pamela S. Trammel, Philippe Schoenborn, Alexander H. Owens
  • Publication number: 20030040135
    Abstract: A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Pamela S. Trammel, Jonathan G. Bornstein, David H. Menche
  • Publication number: 20030031445
    Abstract: A method of making an optical waveguide structure for an active PLC device having a reduced dn/dt birefringence. The method includes the step of forming a waveguide core layer on a bottom cladding, the waveguide core layer having a higher refractive index than the bottom cladding. The waveguide core layer is then etched to define a waveguide core. A top cladding is subsequently formed over the waveguide core and the bottom cladding. The top cladding also has a lower refractive index than the waveguide core. The top cladding is then etched to define a first trench and a second trench parallel to the waveguide core. The first trench and the second trench are configured to relieve a stress on the waveguide core. This stress can be induced by a heater, as in a case where the active PLC is a thermo-optic PLC. The first trench and the second trench can extend from an upper surface of the top cladding to an upper surface of the bottom cladding.
    Type: Application
    Filed: August 10, 2001
    Publication date: February 13, 2003
    Inventors: Farnaz Parhami, Alice Liu, Pamela S. Trammel
  • Publication number: 20030000918
    Abstract: In a planar lightwave circuit, a method of making an optical waveguide that resists core deformation. The method includes a step of forming a core layer on a bottom clad. A waveguide core is formed from the core layer using an etching process. The waveguide core is fabricated to have a higher refractive index than the bottom clad. A silica glass cap layer is then formed over the waveguide core and the bottom clad. A top clad is then formed over the waveguide core, the silica glass cap layer, and the bottom clad. The waveguide core has a higher refractive index than the top clad. The silica glass cap layer maintains the shape of the waveguide core during an anneal process of the top clad. The silica glass cap layer can be deposited using PECVD (plasma enhanced chemical vapor deposition). The silica glass cap layer can be between 0.3 to 2 microns thick. The silica glass cap layer can be undoped silica glass.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Nizar S. Kheraj, Pamela S. Trammel, Fan Zhong, Jonathan G. Bornstein
  • Patent number: 5468342
    Abstract: A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: November 21, 1995
    Assignee: Cypress Semiconductor Corp.
    Inventors: James E. Nulty, Pamela S. Trammel