Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: A coherence controller is included in a module which includes a plurality of multiprocessor units, each of which contains a main memory and processors equipped with respective cache memories. The module may be one of a plurality of similarly constructed modules connected by a router or other type of switching device. The coherence controller in each module includes a cache filter directory having a first filter directory for guaranteeing coherence between the local main memory and the cache memory in each of the processors of the module, and an external port connected to at least one of the other modules. The cache filter directory also includes a complementary filter directory, which tracks locations of lines or blocks of the local main memory copied from the module into other modules, and for guaranteeing coherence between the local main memory and the cache in each of the processors of the module and the other modules.

Abstract: The large-scale symmetric multiprocessor server with a multimodule architecture includes N identical multiprocessor modules 50, 51, 52, 53. The module 50 includes a plurality of multiprocessors 60, 61, 62, 63 equipped with a cache memory and at least one main memory connected to a coherence controller 64 that includes an external port 99 connected to at least one of the multiprocessor modules 51, 52, 53 outside the module 50 and a cache filter directory 84 SF/ED designed to guarantee coherence between the mass memory and the cache memories of the modules, the cache filter directory 84 including a local presence vector 86 that keeps track of the memory lines or blocks copied into the cache memories of the module 50 and an extension 88 that keeps track of the coordinates of the memory lines or blocks copied from the local module 50 to an external module 51, 52, 53.