Abstract: An ultrasonic method and system for simultaneously measuring lubrication film thickness and liner wear of sliding bearings. The method includes: installing an ultrasonic sensor on a bearing bush; sending, by a processor, signals to an ultrasonic pulser-receiver to generate voltage pulses to excite the ultrasonic sensor to generate ultrasonic pulses; collecting an echo signal of an unworn liner-air interface as a reference signal Ba(f); collecting an echo signal of worn liner-lubrication film interface as to-be-measured signal Bow(f); obtaining an amplitude spectrum |Ba(f)| and a phase spectrum ?Baof Ba(f), an amplitude spectrum |Bow(f)| and a phase spectrum ?Bow(f) of Bow(f) by FFT; calculating an amplitude spectrum |Rw(f)|, and a phase spectrum ?Rw(f) of a reflection coefficient; based on |Rw(f)|, calculating lubrication film thickness d via a resonance model or a spring model; and based on ?Rw(f), calculating liner worn thickness via wear model under different film thicknesses.

Abstract: The present disclosure provides D flip-flops and signal driving methods using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit configured to input a first clock signal, a first data signal, a second data signal and a third data signal and generate a clock pulse signal. The clock pulse signal responds a rising-edge and a falling-edge of the first clock signal. The pulse clock signal is a pulse signal when the first data signal is opposite to the second data signal. The D flip-flop also includes a latching circuit configured to sample and transfer the first data signal and a data signal opposite to the first data signal to be used as the second signal and a fourth data signal respectively when the clock signal is at the high level.

Abstract: The present disclosure provides D flip-flops and signal driving methods using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit configured to input a first clock signal, a first data signal, a second data signal and a third data signal and generate a clock pulse signal. The clock pulse signal responds a rising-edge and a falling-edge of the first clock signal. The pulse clock signal is a pulse signal when the first data signal is opposite to the second data signal. The D flip-flop also includes a latching circuit configured to sample and transfer the first data signal and a data signal opposite to the first data signal to be used as the second signal and a fourth data signal respectively when the clock signal is at the high level.