Abstract: A method and a device of intra-chip routing of neural tasks for an operating system of a brain-inspired computer are provided. The method includes determining an area defined by target cores, and determining target cores in a row furthest from an edge routing area; determining whether the target cores need to be configured with relay routing; searching nearest edge routing cores in the edge routing area for all the target cores in the area defined by the target cores; configuring the target cores in a far-to-near principle; and searching relay routing cores and the nearest edge routing cores by a shortest path manner and a maximum step length of a single routing manner.

Abstract: A neural network on-chip mapping method and apparatus based on a tabu search algorithm are provided. The method includes: constructing a tabu search table and using a heuristic-based iterative search process to select local computing cores of a network-on-chip as candidates, establishing an integer programming model and solving an optimal solution, continuously reducing an objective cost function of a mapping solution by loop iteration, and finally obtaining an approximately optimal deployment scheme.

Abstract: A neural model storage system and method for an operating system of a brain-inspired computer are provided. The method includes: storing a neural model on three computing nodes, selecting the computing nodes by dynamically calculating a weight according to the number of idle cores of the first computing node, the number of failures of the first computing node, and failure time of the first computing node in each failure thereof, reading the neural model in the same computing node or cross-computing node, recovering from failures of non-master nodes, recovering from failures of the master node, and recovering from a whole machine restart or failure.

Abstract: A method and a device of intra-chip routing of neural tasks for an operating system of a brain-inspired computer are provided. The method includes determining an area defined by target cores, and determining target cores in a row furthest from an edge routing area; determining whether the target cores need to be configured with relay routing; searching nearest edge routing cores in the edge routing area for all the target cores in the area defined by the target cores; configuring the target cores in a far-to-near principle; and searching relay routing cores and the nearest edge routing cores by a shortest path manner and a maximum step length of a single routing manner.