Patents by Inventor Panagiotis Velentzas
Panagiotis Velentzas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989816Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.Type: GrantFiled: February 25, 2022Date of Patent: May 21, 2024Assignee: Imagination Technologies LimitedInventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20240119662Abstract: Methods and graphics processing units for processing a plurality of fragments in a graphics processing system. A received first fragment is processed by performing an early depth test with hidden surface removal logic using a depth buffer; in response to the first fragment passing the early depth test, executing one or more instructions of a shader program for the first fragment on the processing logic to determine the property of the first fragment; and after the determination of the property of the first fragment, performing a late depth test on the first fragment with the hidden surface removal logic using the depth buffer. After said receiving a first fragment, a second fragment to be processed is received, wherein the second fragment does not have a shader-dependent property. The second fragment is processed by, before said late depth test is performed on the first fragment, performing an early depth test on the second fragment with the hidden surface removal logic.Type: ApplicationFiled: June 22, 2023Publication date: April 11, 2024Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Patent number: 11922555Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: GrantFiled: March 15, 2023Date of Patent: March 5, 2024Assignee: Imagination Technologies LimitedInventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Publication number: 20230385981Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Publication number: 20230297422Abstract: Logic includes a task builder for building tasks comprising data items, a task scheduler for scheduling tasks for processing by a parallel processor, a data store arranged to map content of each data item to an item ID, and a linked-list RAM comprising an entry for each item ID. For each new data item, the task builder creates a new task by starting a new linked list, or adds the data item to an existing linked list. In each linked list, the entry for each data item records a pointer to a next item ID in the list. The task builder indicates when any of the tasks is ready for scheduling. The task scheduler identifies a ready task based on the indication from the task builder, and in response follows the pointers in the respective linked list in order to schedule the data items of the task for processing.Type: ApplicationFiled: April 11, 2023Publication date: September 21, 2023Inventors: Alistair Goudie, Panagiotis Velentzas
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Patent number: 11727525Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: GrantFiled: May 28, 2021Date of Patent: August 15, 2023Assignee: Imagination Technologies LimitedInventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Publication number: 20230252711Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.Type: ApplicationFiled: March 7, 2023Publication date: August 10, 2023Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Publication number: 20230215095Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: ApplicationFiled: March 15, 2023Publication date: July 6, 2023Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Patent number: 11640318Abstract: Logic includes a task builder for building tasks comprising data items, a task scheduler for scheduling tasks for processing by a parallel processor, a data store arranged to map content of each data item to an item ID, and a linked-list RAM comprising an entry for each item ID. For each new data item, the task builder creates a new task by starting a new linked list, or adds the data item to an existing linked list. In each linked list, the entry for each data item records a pointer to a next item ID in the list. The task builder indicates when any of the tasks is ready for scheduling. The task scheduler identifies a ready task based on the indication from the task builder, and in response follows the pointers in the respective linked list in order to schedule the data items of the task for processing.Type: GrantFiled: September 30, 2021Date of Patent: May 2, 2023Assignee: Imagination Technologies LimitedInventors: Alistair Goudie, Panagiotis Velentzas
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Patent number: 11610358Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: GrantFiled: February 6, 2021Date of Patent: March 21, 2023Assignee: Imagination Technologies LimitedInventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Patent number: 11600034Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.Type: GrantFiled: February 8, 2021Date of Patent: March 7, 2023Assignee: Imagination Technologies LimitedInventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Publication number: 20230016927Abstract: A method of scheduling processing in a ray tracing system gathers child rays into a child task, assigns priority to the child task on the basis that one or more child rays of the child task are derived from a task to which priority has been assigned, and schedules the child task for processing in preference to one or more other tasks to be scheduled to which priority has not been assigned.Type: ApplicationFiled: June 28, 2022Publication date: January 19, 2023Inventors: Alistair Goudie, Panagiotis Velentzas
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Publication number: 20230004437Abstract: A method of managing resources in a graphics processing pipeline includes conditionally suspending a task when the task reaches a phase boundary during execution of a program within a texture/shading unit. Suspending the task comprises freeing resources allocated to the task and resources are subsequently re-allocated to the task, such that the task is ready to continue execution, only after determining that the conditions associated with un-suspending the task are satisfied.Type: ApplicationFiled: February 23, 2022Publication date: January 5, 2023Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20220405998Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.Type: ApplicationFiled: February 25, 2022Publication date: December 22, 2022Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20220269527Abstract: A method of repacking tasks in a graphics pipeline includes, in response to a task reaching a checkpoint in a program, determining if the task is eligible for repacking. If the task is eligible for repacking, the task is de-scheduled and it is determined whether repacking conditions are satisfied. In the event that the repacking conditions are satisfied, the method looks for a pair of compatible and non-conflicting tasks at the checkpoint. If such a pair of tasks are found, one or more instances are transferred between the pair of tasks.Type: ApplicationFiled: February 23, 2022Publication date: August 25, 2022Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20220114016Abstract: Logic includes a task builder for building tasks comprising data items, a task scheduler for scheduling tasks for processing by a parallel processor, a data store arranged to map content of each data item to an item ID, and a linked-list RAM comprising an entry for each item ID. For each new data item, the task builder creates a new task by starting a new linked list, or adds the data item to an existing linked list. In each linked list, the entry for each data item records a pointer to a next item ID in the list. The task builder indicates when any of the tasks is ready for scheduling. The task scheduler identifies a ready task based on the indication from the task builder, and in response follows the pointers in the respective linked list in order to schedule the data items of the task for processing.Type: ApplicationFiled: September 30, 2021Publication date: April 14, 2022Inventors: Alistair Goudie, Panagiotis Velentzas
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Publication number: 20220012841Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: ApplicationFiled: May 28, 2021Publication date: January 13, 2022Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Publication number: 20210256746Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.Type: ApplicationFiled: February 6, 2021Publication date: August 19, 2021Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
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Publication number: 20210248805Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.Type: ApplicationFiled: February 8, 2021Publication date: August 12, 2021Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang